TSB41BA3APFP datasheet(44/66 Pages) TI

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TSB41BA3A

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS618B − JUNE 2004 − REVISED AUGUST 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

transmit

When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus.

If the PHY wins arbitration for the serial bus, then the PHY-LLC interface bus is granted to the LLC by asserting

the grant state (11b) on the CTL terminals for one PCLK cycle, followed by idle for one clock cycle. The LLC

then takes control of the bus by asserting either idle (00b), hold (01b) or transmit (10b) on the CTL terminals.

Unless the LLC is immediately releasing the interface, the LLC may assert the idle state for at most one clock

before it must assert either hold or transmit on the CTL terminals. The hold state is used by the LLC to retain

control of the bus while it prepares data for transmission. The LLC may assert hold for zero or more clock cycles

(that is, the LLC need not assert hold before transmit). The PHY asserts data-prefix on the serial bus during this

time.

When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the first

bits of packet data on the D lines. The transmit state is held on the CTL terminals until the last bits of data have

been sent. The LLC then asserts either hold or idle on the CTL terminals for one clock cycle and then asserts

idle for one additional cycle before releasing the interface bus and putting the CTL and D terminals in a

high-impedance state. The PHY then regains control of the interface bus.

The hold state asserted at the end-of-packet transmission indicates to the PHY that the LLC requests to send

another packet (concatenated packet) without releasing the serial bus. The PHY responds to this concatenation

request by waiting the required minimum packet separation time and then asserting grant as before. This

function may be used to send a unified response after sending an acknowledge or to send consecutive

isochronous packets during a single isochronous period. Unless multispeed concatenation is enabled, all

packets transmitted during a single bus ownership must be of the same speed (since the speed of the packet

is set before the first packet). If multispeed concatenation is enabled (when the EMSC bit of PHY register 5 is

set), then the LLC must specify the speed code of the next concatenated packet on the D terminals when it

asserts hold on the CTL terminals at the end of a packet. The encoding for this speed code is the same as the

speed code that precedes received packet data as given in Table 21.

After sending the last packet for the current bus ownership, the LLC releases the bus by asserting idle on the

CTL terminals for two clock cycles. The PHY begins asserting idle on the CTL terminals one clock after sampling

idle from the link. Note that whenever the D and CTL terminals change direction between the PHY and the LLC,

there is an extra clock period allowed so that both sides of the interface can operate on registered versions of

the interface signals.

(g)

(e)/(f)

(d)

(c)

(b)

(a)

d0, d1, . . .

Link Controls CTL and D

PHY High-Impedance CTL and D Outputs

D0–D7

CTL0, CTL1

SYSCLK

NOTE A: SPD = Speed code, see Table 21. d0–dn = Packet data

00/01

00/SP

Figure 17. Normal Packet Transmission Timing

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