TSB41BA3APFP datasheet(12/66 Pages) TI

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TSB41BA3A

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS618B − JUNE 2004 − REVISED AUGUST 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

NAME

TYPE

PFP

NO.

GGM

NO.

I/O

DESCRIPTION

CMOS

Port sleep/mode selection terminal 3. On hardware reset, this terminal when used with the

other 5 selection pins allows the user to select the speed and mode of the ports. See

Table 1. Programming is done by tying the terminals high through a 1-k

Ω or smaller resistor

or by tying directly to ground through a 1-k

Ω or smaller resistor. A bus holder is built into this

terminal.

CMOS

E10

Port sleep/mode selection terminal 4. On hardware reset, this terminal when used with the

other 5 selection pins allows the user to select the speed and mode of the ports. See

Table 1. Programming is done by tying the terminals high through a 1-k

Ω or smaller resistor

or by tying directly to ground through a 1-k

Ω or smaller resistor. A bus holder is built into this

terminal.

S5_LKON

CMOS

I/O

Port sleep/mode selection terminal 5 and link-on output. This terminal may be connected to

the link-on input terminal of the LLC through a 1-k

Ω resistor if the link-on input is available

on the link layer.

On hardware reset, this terminal when used with the other 5 selection pins allows the user

to select the speed and mode of the ports. See Table 1. A bus holder is built into this

terminal.

After hardware reset, this terminal is the link-on output, which notifies the LLC or other

power-up logic to power up and become active. The link-on output is a square wave signal

with a period of approximately 163 ns (8 PCLK cycles) when active. The link-on output is

otherwise driven low, except during hardware reset when it is high impedance.

The link-on output is activated if the LLC is inactive (the LPS input inactive or the LCtrl bit

cleared) and when one:

a) The PHY receives a link-on PHY packet addressed to this node

b) The PEI (port-event interrupt) register bit is 1, or

c) Any of the CTOI (configuration-timeout interrupt), CPSI (cable-power-status interrupt),

d) The PHY is power cycled and the power class is 0 through 4

Once activated, the link-on output is active until the LLC becomes active (both the LPS

input active and the LCtrl bit set). The PHY also deasserts the link-on output when a bus-

reset occurs unless the link-on output is otherwise active because one of the interrupt bits

is set (that is, the link-on output is active due solely to the reception of a link-on PHY

packet).

In the case of power cycling the PHY, the LKON signal must stop after 167

µs if the above

conditions have not been met.

NOTE: If an interrupt condition exists which otherwise causes the link-on output to be

activated if the LLC were inactive, then the link-on output is activated when the LLC

subsequently becomes inactive.

TESTM

CMOS

Test control input. This input is used in the manufacturing test of the TSB41BA3A. For

normal use this terminal must be pulled high through a 1-k

Ω resistor to VDD.

TPA0−

TPA0+

TPB0−

TPB0+

Cable

45,

46,

41,

I/O

Port 0 twisted-pair differential-signal terminals. Board traces from each pair of positive

and negative differential signal terminals must be kept matched and as short as

possible to the external load resistors and to the cable connector. Request the S800

1394b layout recommendations document from your Texas Instruments representative.

TPA1−

TPA1+

TPB1−

TPB1+

Cable

I/O

Port 1 twisted-pair differential-signal terminals. Board traces from each pair of positive

and negative differential signal terminals must be kept matched and as short as

possible to the external load resistors and to the cable connector. Request the S800

1394b layout recommendations document from your Texas Instruments representative.

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