MPC7457 datasheet(23/68 Pages) FREESCALE

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MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

Electrical and Thermal Characteristics

5.2.4.1

Effects of L3OHCR Settings on L3 Bus AC Specifications

The AC timing of the L3 interface can be adjusted using the L3 Output Hold Control Register (L3OCHR). Each

field controls the timing for a group of signals. The AC timing specifications presented herein represent the AC

timing when the register contains the default value of 0x0000_0000. Incrementing a field delays the associated

signals, increasing the output valid time and hold time of the affected signals. In the special case of delaying an

L3_CLK signal, the net effect is to decrease the output valid and output hold times of all signals being latched

relative to that clock signal. The amount of delay added is summarized in Table 12. Note that these settings affect

output timing parameters only and do not impact input timing parameters of the L3 bus in any way.

Table 11. Sample Points Calculation Parameters

Parameter

Symbol

Max

Unit

Notes

Delay from processor clock to internal_L3_CLK

tAC

3/4

tL3_CLK

Delay from internal_L3_CLK to L3_CLK[n] output pins

tCO

Delay from L3_ECHO_CLK[n] to receive latch

tECI

Notes:

1. This specification describes a logical offset between the internal clock edge used to launch the L3 address and control

signals (this clock edge is phase-aligned with the processor clock edge) and the internal clock edge used to launch the

L3_CLK[n] signals. With proper board routing, this offset ensures that the L3_CLK[n] edge will arrive at the SRAM within a

valid address window and provide adequate setup and hold time. This offset is reflected in the L3 bus interface AC timing

specifications, but must also be separately accounted for in the calculation of sample points and, thus, is specified here.

2. This specification is the delay from a rising or falling edge on the internal_L3_CLK signal to the corresponding rising or falling

edge at the L3CLK[n] pins.

3. This specification is the delay from a rising or falling edge of L3_ECHO_CLK[n] to data valid and ready to be sampled from

the FIFO.

Table 12. Effect of L3OHCR Settings on L3 Bus AC Timing

At recommended operating conditions. See Table 4.

Field Name1

Affected Signals

Value

Output Valid Time

Output Hold Time

Unit

Notes

Parameter

Symbol 2

Change 3

Parameter

Symbol 2

Change 3

L3AOH

L3_ADDR[18:0],

L3_CNTL[0:1]

0b00

tL3CHOV

tL3CHOX

0b01

+50

0b10

+100

0b11

+150

L3CLKn_OH

All signals latched by

SRAM connected to

L3_CLKn

0b000

tL3CHOV,

tL3CHDV,

tL3CLDV

tL3CHOX,

tL3CHDX,

tL3CLDX,

0b001

– 50

0b010

– 100

0b011

– 150

0b100

– 200

0b101

– 250

0b110

– 300

0b111

– 350

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