MPC7457 datasheet(5/68 Pages) FREESCALE

5 / 68 page

MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

Features

— Tracks unresolved branches and flushes instructions after a mispredicted branch

— Retires as many as three instructions per clock cycle

•

Separate on-chip L1 instruction and data caches (Harvard architecture)

— 32-Kbyte, eight-way set associative instruction and data caches

— Pseudo least recently used (PLRU) replacement algorithm

— 32-byte (eight-word) L1 cache block

— Physically indexed/physical tags

— Cache write-back or write-through operation programmable on a per-page or per-block basis

— Instruction cache can provide four instructions per clock cycle; data cache can provide four words per

clock cycle

— Caches can be disabled in software.

— Caches can be locked in software.

— MESI data cache coherency maintained in hardware

— Separate copy of data cache tags for efficient snooping

— Parity support on cache and tags

— No snooping of instruction cache except for icbi instruction

— Data cache supports AltiVec LRU and transient instructions

— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word forwarding

is used for AltiVec loads and instruction fetches. Other accesses use critical double-word forwarding.

•

Level 2 (L2) cache interface

— On-chip, 512-Kbyte, eight-way set associative unified instruction and data cache

— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches

— A total nine-cycle load latency for an L1 data cache miss that hits in L2

— PLRU replacement algorithm

— Cache write-back or write-through operation programmable on a per-page or per-block basis

— 64-byte, two-sectored line size

— Parity support on cache

•

Level 3 (L3) cache interface (not implemented on MPC7447)

— Provides critical double-word forwarding to the requesting unit

— Internal L3 cache controller and tags

— External data SRAMs

— Support for 1-, 2-, and 4-Mbyte (MB) total SRAM space

— Support for 1- or 2-MB of cache space

— Cache write-back or write-through operation programmable on a per-page or per-block basis

— 64-byte (1-MB) or 128-byte (2-MB) sectored line size

— Private memory capability for half (1 MB minimum) or all of the L3 SRAM space for a total of 1-, 2-,

or 4-MB of private memory

— Supports MSUG2 dual data rate (DDR) synchronous burst SRAMs, PB2 pipelined synchronous burst

SRAMs, and pipelined (register-register) late write synchronous burst SRAMs

— Supports parity on cache and tags

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