MPC7457 datasheet(47/68 Pages) FREESCALE

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MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

System Design Information

This section provides system and thermal design recommendations for successful application of the MPC7457.

9.1

Clocks

The following sections provide more detailed information regarding the clocking of the MPC7457.

9.1.1

Core Clocks and PLL Configuration

The MPC7457 PLL is configured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus) frequency, the PLL

configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the

MPC7457 is shown in Table 18 for a set of example frequencies. In this example, shaded cells represent settings

that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with the 1-GHz

column in Table 8. Note that these configurations were different in some earlier MPC7450-family devices and care

should be taken when upgrading to the MPC7457 to verify the correct PLL settings for an application.

Table 18. MPC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts

PLL_CFG[0:4]

Bus-to-

Core

Multiplier

Core-to-

VCO

Multiplier

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus (SYSCLK) Frequency

33.3

MHz

66.6

MHz

100

MHz

133

MHz

167

MHz

01000

10000

10100

667

(1333)

10110

667

(1333)

835

(1670)

10010

5.5x

733

(1466)

919

(1837)

11010

600

(1200)

800

(1600)

1002

(2004)

01010

6.5x

650

(1300)

866

(1730)

1086

(2171)

00100

700

(1400)

931

(1862)

1169

(2338)

00010

7.5x

623

(1245)

750

(1500)

1000

(2000)

1253

(2505)

11000

600

(1200)

664

(1328)

800

(1600)

1064

(2128)

01100

8.5x

638

(1276)

706

(1412)

850

(1700)

1131

(2261)

01111

600

(1200)

675

(1350)

747

(1494)

900

(1800)

1197

(2394)

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