MPC7457 datasheet(15/68 Pages) FREESCALE

15 / 68 page

MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

Electrical and Thermal Characteristics

5.2

AC Electrical Characteristics

This section provides the AC electrical characteristics for the MPC7457. After fabrication, functional parts are

sorted by maximum processor core frequency as shown in Section 1.5.2.1, “Clock AC Specifications,” and tested

for conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus

(SYSCLK) frequency and the settings of the PLL_CFG[0:4] signals. Parts are sold by maximum processor core

frequency; see Section 1.11, “Ordering Information.”

5.2.1

Clock AC Specifications

Table 8 provides the clock AC timing specifications as defined in Figure 6 and represents the tested operating

frequencies of the devices. The maximum system bus frequency, fSYSCLK, given in Table 8 is considered a practical

maximum in a typical single-processor system. The actual maximum SYSCLK frequency for any application of the

MPC7457 will be a function of the AC timings of the MPC7457, the AC timings for the system controller, bus

loading, printed-circuit board topology, trace lengths, and so forth, and may be less than the value given in Table 8.

For information regarding the use of spread spectrum clock generators, see Section 9.1.3, “System Bus Clock

(SYSCLK) and Spread Spectrum Sources.” PLL configuration and bus-to-core multiplier information is found in

Section 9.1.1, “Core Clocks and PLL Configuration.”

Deep Sleep Mode (PLL Disabled)

Typical

5.0

1, 2

Notes:

1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power (OVDD and

GVDD) or PLL supply power (AVDD). OVDD and GVDD power is system dependent, but is typically <5% of VDD power. Worst

case power consumption for AVDD < 3 mW.

2. Typical power is an average value measured at the nominal recommended VDD (see Table 4) and 65°C while running the

Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.

3. Maximum power is the average measured at nominal VDD and maximum operating junction temperature (see Table 4) while

running an entirely cache-resident, contrived sequence of instructions which keep all the execution units maximally busy.

4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep mode. As a

result, power consumption for this mode is not tested.

Table 8. Clock AC Timing Specifications

At recommended operating conditions. See Table 4.

Characteristic

Symbol

Maximum Processor Core Frequency

Unit

Notes

867 MHz

1000 MHz

1200 MHz

1267 MHz

Min

Max

Min

Max

Min

Max

Min

Max

Processor frequency

fcore

600

867

600

1000

600

1200

600

1267

MHz

VCO frequency

fVCO

1200

1733

1200

2000

1200

2400

1200

2534

MHz

SYSCLK frequency

fSYSCLK

167

MHz

1, 2

Table 7. Power Consumption for MPC7457 (continued)

Processor (CPU) Frequency

Unit

Notes

867 MHz

1000 MHz

1200 MHz

1267 MHz

MPC7457 датащи(PDF) 15 Page - Freescale Semiconductor, Inc

MPC7457 датащи(HTML) 15 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

датащи скачать

ссылки URL