MPC7457 datasheet(12/68 Pages) FREESCALE

12 / 68 page

MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 4 provides the recommended operating conditions for the MPC7457.

Table 3. Input Threshold Voltage Setting

BVSEL Signal

Processor Bus Input Threshold

is Relative to:

L3VSEL Signal 1

L3 Bus Input Threshold is

Relative to:

Notes

1.8 V

2, 3

¬HRESET

Not Available

¬HRESET

1.5 V

2, 4

HRESET

2.5 V

HRESET

2.5 V

Notes:

Not implemented on MPC7447.

Caution: The input threshold selection must agree with the OVDD/GVDD voltages supplied. See notes in Table 2.

If used, pull-down resistors should be less than 250

Ω.

Applicable to L3 bus interface only. ¬HRESET is the inverse of HRESET.

Table 4. Recommended Operating Conditions 1

Characteristic

Symbol

Recommended Value

Unit

Notes

Min

Max

Core supply voltage

VDD

1.3 V ± 50 mV

PLL supply voltage

AVDD

1.3 V ± 50 mV

Processor bus supply voltage

BVSEL = 0

OVDD

1.8 V ± 5%

BVSEL = HRESET or OVDD

OVDD

2.5 V ± 5%

L3 bus supply voltage

L3VSEL = 0

GVDD

1.8 V ± 5%

L3VSEL = HRESET or GVDD

GVDD

2.5 V ± 5%

L3VSEL = ¬HRESET

GVDD

1.5 V ± 5%

Input voltage

Processor bus

Vin

GND

OVDD

L3 bus

Vin

GND

GVDD

JTAG signals

Vin

GND

OVDD

Die-junction temperature

105

°C

Notes:

These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not

guaranteed.

This voltage is the input to the filter discussed in Section 9.2, “PLL Power Supply Filtering,” and not necessarily the voltage

at the AVDD pin, which may be reduced from VDD by the filter.

¬HRESET is the inverse of HRESET.

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