MPC7457 datasheet(52/68 Pages) FREESCALE

52 / 68 page

MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

System Design Information

9.5

Output Buffer DC Impedance

The MPC7457 processor bus and L3 I/O drivers are characterized over process, voltage, and temperature. To

measure Z0, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of each resistor

is varied until the pad voltage is OVDD/2 (see Figure 23).

The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When

data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the pad equals OVDD/2. RN

then becomes the resistance of the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and

RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP

and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2.

Figure 25. Driver Impedance Measurement

Table 21 summarizes the signal impedance results. The impedance increases with junction temperature and is

relatively unaffected by bus voltage.

9.6

Pull-Up/Pull-Down Resistor Requirements

The MPC7457 requires high-resistive (weak: 4.7-kΩ) pull-up resistors on several control pins of the bus interface to

maintain the control signals in the negated state after they have been actively negated and released by the MPC7457

or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1.

Some pins designated as being for factory test must be pulled up to OVDD or down to GND to ensure proper device

operation. For the MPC7447, 360 BGA, the pins that must be pulled up to OVDD are: LSSD_MODE and TEST[0:3];

the pins that must be pulled down to GND are: L1_TSTCLK and TEST[4]. For the MPC7457, 483 BGA, the pins

that must be pulled up to OVDD are: LSSD_MODE and TEST[0:5]; the pins that must be pulled down are:

Table 21. Impedance Characteristics

VDD = 1.5 V, OVDD = 1.8 V ± 5%, Tj = 5°–85°C

Impedance

Processor Bus

L3 Bus

Unit

Typical

33–42

34–42

Ω

Maximum

31–51

32–44

Ω

OVDD

OGND

Pad

Data

SW1

SW2

MPC7457 датащи(PDF) 52 Page - Freescale Semiconductor, Inc

MPC7457 датащи(HTML) 52 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

датащи скачать

ссылки URL