MPC7457 datasheet(53/68 Pages) FREESCALE

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MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

System Design Information

L1_TSTCLK and TEST[6]. The CKSTP_IN signal should likewise be pulled up through a pull-up resistor (weak or

stronger: 4.7–1 kΩ) to prevent erroneous assertions of this signal.

In addition, the MPC7457 has one open-drain style output that requires a pull-up resistor (weak or stronger:

4.7–1 kΩ) if it is used by the system. This pin is CKSTP_OUT.

If pull-down resistors are used to configure BVSEL or L3VSEL, the resistors should be less than 250 Ω (see

Table 16). Because PLL_CFG[0:4] must remain stable during normal operation, strong pull-up and pull-down

resistors (1 kΩ or less) are recommended to configure these signals in order to protect against erroneous switching

due to ground bounce, power supply noise or noise coupling.

During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may,

therefore, float in the high-impedance state for relatively long periods of time. Because the MPC7457 must

continually monitor these signals for snooping, this float condition may cause excessive power draw by the input

receivers on the MPC7457 or by other receivers in the system. These signals can be pulled up through weak (10-kΩ)

pull-up resistors by the system, address bus driven mode enabled (see the MPC7450 RISC Microprocessor Family

Users’ Manual for more information about this mode), or they may be otherwise driven by the system during

inactive periods of the bus to avoid this additional power draw. Preliminary studies have shown the additional power

draw by the MPC7457 input receivers to be negligible and, in any event, none of these measures are necessary for

proper device operation. The snooped address and transfer attribute inputs are: A[0:35], AP[0:4], TT[0:4], CI, WT,

and GBL.

If extended addressing is not used, A[0:3] are unused and must be pulled low to GND through weak pull-down

resistors. If the MPC7457 is in 60x bus mode, DTI[0:3] must be pulled low to GND through weak pull-down

resistors.

The data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not

require pull-up resistors on the bus. Other data bus receivers in the system, however, may require pull-ups, or that

those signals be otherwise driven by the system during inactive periods by the system. The data bus signals are:

D[0:63] and DP[0:7].

If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the

input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left

unconnected by the system. If all parity generation is disabled through HID0, all parity checking should also be

disabled through HID0, and all parity pins may be left unconnected by the system.

The L3 interface does not normally require pull-up resistors. Unused L3_ADDR signals are driven low when the

SRAM is configured to be less than 1 M in size via L3CR. For example, L3_ADD[18] will be driven low if the

SRAM size is configured to be 2 M; likewise, L3_ADDR[18:17] will be driven low if the SRAM size is configured

to be 1 M.

9.7

JTAG Configuration Signals

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE

1149.1 specification, but is provided on all processors that implement the PowerPC architecture. While it is possible

to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset

performance will be obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is

also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not

practical.

The COP function of these processors allows a remote computer system (typically, a PC with dedicated hardware

and debugging software) to access and control the internal operations of the processor. The COP interface connects

primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port

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