MPC7457 datasheet(25/68 Pages) FREESCALE

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MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 13. L3 Bus Interface AC Timing Specifications for MSUG2

At recommended operating conditions. See Table 4.

Parameter

Symbol

Device Revision (L3 I/O Voltage) 9

Unit

Notes

Rev 1.1. (All I/O Modes)

Rev 1.2 (1.5-V I/O Mode)

Rev 1.2

(1.8-, 2.5-V I/O Modes)

Min

Max

Min

Max

L3_CLK rise and fall time

tL3CR, tL3CF

—

0.75

—

0.75

Setup times: Data and parity

tL3DVEH,

tL3DVEL

(– tL3CLK/4)

+ 0.90

—

(– tL3CLK/4)

+ 0.70

—

2, 3, 4

Input hold times: Data and parity

tL3DXEH,

tL3DXEL

(tL3CLK/4)

+ 0.85

—

(tL3CLK/4)

+ 0.70

—

2, 4

Valid times: Data and parity

tL3CHDV,

tL3CLDV

—

(– tL3CLK/4)

+ 0.60

—

(– tL3CLK/4)

+ 0.50

5, 6,

7, 8

Valid times: All other outputs

tL3CHOV

—

(tL3CLK/4)

+ 0.65

—

(tL3CLK/4)

+ 0.65

5, 7, 8

Output hold times: Data and parity

tL3CHDX,

tL3CLDX,

(tL3CLK/4)

– 0.60

—

(tL3CLK/4)

– 0.50

—

5, 6,

7, 8

Output hold times: All other outputs

tL3CHOX

(tL3CLK/4)

– 0.50

—

(tL3CLK/4)

– 0.50

—

5, 7, 8

L3_CLK to high impedance: Data

and parity

tL3CLDZ

—

(– tL3CLK/4)

+ 0.60

—

(– tL3CLK/4)

+ 0.60

L3_CLK to high impedance: All

other outputs

tL3CHOZ

—

(tL3CLK/4)

+ 0.65

—

(tL3CLK/4)

+ 0.65

Notes:

Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.

For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the

rising or falling edge of the input L3_ECHO_CLKn (see Figure 10). Input timings are measured at the pins.

For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 10. For consistency with other

input setup time specifications, this will be treated as negative input setup time.

tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the MPC7457 can latch an input signal that is

valid for only a short time before and a short time after the midpoint between the rising and falling (or falling and rising)

edges of L3_ECHO_CLKn at any frequency.

All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the falling) edge

of L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume

a purely resistive 50-

Ω load (see Figure 8).

For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 10. For consistency with other output

valid time specifications, this will be treated as negative output valid time.

tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched

by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid and output hold

times such that the specified output signal will be valid for approximately one L3_CLK period starting three-fourths of a clock

before the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled.

Assumes default value of L3OHCR. See Section 5.2.4.1, “Effects of L3OHCR Settings on L3 Bus AC Specifications,” for

more information.

L3 I/O voltage mode must be configured by L3VSEL as described in Table 3, and voltage supplied at GVDD must match

mode selected as specified in Table 4. See Table 23 for revision level information and part marking.

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