AD9886SLASHPCB datasheet(29/32 Pages) AD

29 / 32 page

REV. 0

AD9886

–29–

Data is read from the control registers of the AD9886 in a similar

manner. Reading requires two data transfer operations:

The base address must be written with the R/

W bit of the slave

address byte LOW to set up a sequential read operation.

Reading (the R/

W bit of the slave address byte HIGH) begins at

the previously established base address. The address of the read

To terminate a read/write sequence to the AD9886, a stop sig-

nal must be sent. A stop signal comprises a LOW-to-HIGH

transition of SDA while SCL is HIGH.

A repeated start signal occurs when the master device driving

the serial interface generates a start signal without first generat-

ing a stop signal to terminate the current communication. This

is used to change the mode of communication (read, write)

between the slave and master without releasing the serial inter-

face lines.

Serial Interface Read/Write Examples

Write to one control register

➥Start signal

➥Slave Address byte (R/W bit = LOW)

➥Base Address byte

➥Data byte to base address

➥Stop signal

Write to four consecutive control registers

➥Start signal

➥Slave Address byte (R/W bit = LOW)

➥Base Address byte

➥Data byte to base address

➥Data byte to (base address + 1)

➥Data byte to (base address + 2)

➥Data byte to (base address + 3)

➥Stop signal

Read from one control register

➥Start signal

➥Slave Address byte (R/W bit = LOW)

➥Base Address byte

➥Start signal

➥Slave Address byte (R/W bit = HIGH)

➥Data byte from base address

➥Stop signal

Read from four consecutive control registers

➥Start signal

➥Slave Address byte (R/W bit = LOW)

➥Base Address byte

➥Start signal

➥Slave Address byte (R/W bit = HIGH)

➥Data byte from base address

➥Data byte from (base address + 1)

➥Data byte from (base address + 2)

➥Data byte from (base address + 3)

➥Stop signal

BIT 7

SDA

SCL

ACK

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Figure 28. Serial Interface—Typical Byte Transfer

SDA

SCL

tBUFF

tSTAH

tDHO

tDSU

tDAL

tDAH

tSTASU

tSTOSU

Figure 27. Serial Port Read/

Write Timing

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