REV. 0

AD9886

–13–

Table IV. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats

Refresh

Horizontal

Standard

Resolution

Rate

Frequency

Pixel Rate

VCORNGE

CURRENT

VGA

640

× 480

60 Hz

31.5 kHz

25.175 MHz

00

101

72 Hz

37.7 kHz

31.500 MHz

00

101

75 Hz

37.5 kHz

31.500 MHz

00

110

85 Hz

43.3 kHz

36.000 MHz

00

110

SVGA

800

× 600

56 Hz

35.1 kHz

36.000 MHz

00

101

60 Hz

37.9 kHz

40.000 MHz

01

101

72 Hz

48.1 kHz

50.000 MHz

01

101

75 Hz

46.9 kHz

49.500 MHz

01

101

85 Hz

53.7 kHz

56.250 MHz

01

110

XGA

1024

× 768

60 Hz

48.4 kHz

65.000 MHz

01

110

70 Hz

56.5 kHz

75.000 MHz

10

101

75 Hz

60.0 kHz

78.750 MHz

10

101

80 Hz

64.0 kHz

85.500 MHz

10

101

85 Hz

68.3 kHz

94.500 MHz

10

101

SXGA

1280

× 1024

60 Hz

64.0 kHz

108.000 MHz

10

110

75 Hz

80.0 kHz

135.000 MHz

11

110

85 Hz

91.1 kHz

157.500 MHz

*

10

110

UXGA

1600

× 1200

60 Hz

75.0 kHz

162.000 MHz

*

10

110

65 Hz

81.3 kHz

175.500 MHz

*

10

110

70 Hz

87.5 kHz

189.000 MHz

*

10

110

75 Hz

93.8 kHz

202.500 MHz

*

10

110

85 Hz

106.3 kHz

229.500 MHz

*

11

110

*Graphics sampled at one-half the incoming pixel rate using Alternate Pixel Sampling mode.

Table II. VCO Frequency Ranges

Pixel Clock

PV1

PV0

Range (MHz)

(MHz/V)

0

0

12–35

150

0

1

35–70

150

1

0

70–110

150

1

1

110–140

180

3. The 3-Bit Charge Pump Current Register. This register

allows the current that drives the low pass loop filter to be

varied. The possible current values are listed in Table III.

Table III. Charge Pump Current/Control Bits

Ip2

Ip1

Ip0

Current ( A)

00

0

50

0

0

1

100

0

1

0

150

0

1

1

250

1

0

0

350

1

0

1

500

1

1

0

750

1

1

1

1500

4. The 5-Bit Phase Adjust Register. The phase of the generated

sampling clock may be shifted to locate an optimum sam-

pling point within a clock cycle. The Phase Adjust register

provides 32 phase-shift steps of 11.25

° each. The Hsync

signal with an identical phase shift is available through the

HSOUT pin. Phase adjustment is still available if the pixel

clock is being provided externally.

The COAST pin is used to allow the PLL to continue to run

at the same frequency, in the absence of the incoming Hsync

signal. This may be used during the vertical sync period, or

any other time that the Hsync signal is unavailable. The

polarity of the COAST signal may be set through the Coast

Polarity Register. Also, the polarity of the Hsync signal may

be set through the HSYNC Polarity Register. For both

HSYNC and COAST, a value of “1” inverts the signal.