AD9886SLASHPCB datasheet(8/32 Pages) AD

8 / 32 page

REV. 0

AD9886

–8–

Outputs

DRA7-0

Data Output, Red Channel, Port A

DRB7-0

Data Output, Red Channel, Port B

DGA7-0

Data Output, Green Channel, Port A

DGB7-0

Data Output, Green Channel, Port B

DBA7-0

Data Output, Blue Channel, Port A

DBB7-0

Data Output, Blue Channel, Port B

These are the main data outputs. Bit 7 is

the MSB.

Each channel has two ports. When the part is

operated in single-channel mode (DEMUX =

0), all data are presented to Port A, and Port B

is placed in a high-impedance state.

Programming DEMUX to 1 established dual-

channel mode, wherein alternate pixels are

presented to Port A and Port B of each chan-

nel. These will appear simultaneously, two

pixels presented at the time of every second

input pixel, when PAR is set to 1 (parallel

mode). When PAR = 0, pixel data appear

alternately on the two ports, one new sample

with each incoming pixel (interleaved mode).

In dual channel mode, the first pixel after

HSYNC is routed to Port A. The second

pixel goes to Port B, the third to A, etc. This

can be reversed by setting OUTPHASE to 1.

The delay from pixel sampling time to output

is fixed. When the sampling time is changed

by adjusting the PHASE register, the output

timing is shifted as well. The DATACK,

DATACK, and HSOUT outputs are also

moved, so the timing relationship among the

signals is maintained.

DATACK

Data Output Clock

DATACK

Data Output Clock Complement

Differential data clock output signals to be

used to strobe the output data and HSOUT

into external logic.

They are produced by the internal clock gen-

erator and are synchronous with the internal

pixel sampling clock.

When the AD9886 is operated in single-

channel mode, the output frequency is equal

to the pixel sampling frequency. When operat-

ing in dual channel mode, the clock frequency

is one-half the pixel frequency, as is the output

data frequency.

When the sampling time is changed by adjust-

ing the PHASE register, the output timing

is shifted as well. The Data, DATACK,

DATACK, and HSOUT outputs are all

moved, so the timing relationship among the

signals is maintained.

Either or both signals may be used, depend-

ing on the timing mode and interface design

employed.

HSOUT

Horizontal Sync Output

A reconstructed and phase-aligned version of

the Hsync input. Both the polarity and dura-

tion of this output can be programmed via

serial bus registers.

By maintaining alignment with DATACK,

DATACK, and Data, data timing with

respect to horizontal sync can always be

determined.

SOGOUT

Sync-On-Green Slicer Output

This pin can be programmed to output

either the output from the Sync-On-Green

slicer comparator or an unprocessed but

delayed version of the HSYNC input. See

the Sync Block Diagram to view how this

pin is connected.

(Note: Besides slicing off SOG, the output

from this pin receives no additional process-

ing on the AD9886. VSYNC separation is

performed via the sync separator.)

REFOUT

Internal Reference Output

Output from the internal 1.25 V bandgap

reference. This output is intended to drive

relatively light loads. It can drive the AD9886

Reference Input directly, but should be exter-

nally buffered if it is used to drive other loads

as well.

The absolute accuracy of this output is

±4%,

and the temperature coefficient is

±50 ppm,

which is adequate for most AD9886 appli-

cations. If higher accuracy is required, an

external reference may be employed instead.

If an external reference is used, connect this

pin to ground through a 0.1

µF capacitor.

REFIN

Reference Input

The reference input accepts the master refer-

ence voltage for all AD9886 internal circuitry

(1.25 V

±10%). It may be driven directly by

the REFOUT pin. Its high impedance pre-

sents a very light load to the reference source.

This pin should always be bypassed to Ground

with a 0.1

µF capacitor.

FILT

External Filter Connection

For proper operation, the pixel clock genera-

tor PLL requires an external filter. Connect

the filter shown Figure 7 to this pin. For

optimal performance, minimize noise and

parasitics on this node.

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