AD9886SLASHPCB datasheet(21/32 Pages) AD

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AD9886

–21–

Table V. Control Register Map (Continued)

Write and

Hex

Read or

Default

Address

Read Only

Bits

Value

Name

Function

12H

W/R

7:0

*******

Active

Bit 7—AIO: Active Interface Override. If set to Logic 1, the user

Interface

can select the active interface via Bit 6. If set to Logic 0, the active

interface is selected via Bit 3 in Register 11H.

*0******

Bit 6—AIS: Active Interface Select. Logic 0 selects the analog inter-

face as active. Logic 1 selects the digital interface as active. Note:

The indicated interface will be active only if Bit 7 is set to Logic 1

or if both interfaces are active (Bits 6 or 7 and 4 = Logic 1 in

**0*****

Bit 5—Active Hsync Override. If set to Logic 1, the user can select

the Hsync to be used via Bit 4. If set to Logic 0, the active interface

is selected via Bit 2 in Register 11H.

***0****

Bit 4—Active Hsync Select. Logic 0 selects Hsync as the active

sync. Logic 1 selects Sync-on-Green as the active sync. Note: The

indicated Hsync will be used only if Bit 5 is set to Logic 1 or if

both syncs are active (Bits 6, 7 = Logic 1 in Register 11H.)

****0***

Bit 3—Active Vsync Override. If set to Logic 1, the user can select

the Vsync to be used via Bit 2. If set to Logic 0, the active interface

is selected via Bit 1 in Register 11H.

*****0**

Bit 2—Active Vsync Select. Logic 0 selects Raw Vsync as the

output Vsync. Logic 1 selects Sync Separated Vsync as the output

Vsync. Note: The indicated Vsync will be used only if Bit 3 is set

to Logic 1.

******0*

Bit 1—Coast Select. Logic 0 selects the coast input pin to be used for

the PLL coast. Logic 1 selects Vsync to be used for the PLL coast.

*******1

Bit 0—

PWRDN. Full Chip Power-Down, active low. (Logic 0 =

Full Chip Power-Down, Logic 1 = Normal.)

13H

W/R

7:0

00100000

Sync

Sync Separator Threshold—Sets how many pixel clocks the sync

Separator

separator will count to before toggling high or low. This should be

Threshold

set to some number greater than the maximum Hsync or equaliza-

tion pulsewidth.

14H

W/R

7:0

***1****

Control Bits

Bit 4—Test Bit. (Must be set to 1 for proper operation of chip.)

*****0**

Bit 2—Scan Enable. (Logic 0 = Not Enabled, Logic 1 = Enabled.)

******0*

Bit 1—Coast Polarity Override. (Logic 0 = Polarity determined by

chip, Logic 1 = Polarity set by Bit 6 in Register 0Fh.)

*******0

Bit 0– Hsync Polarity Override. (Logic 0 = Polarity determined by

chip, Logic 1 = Polarity set by Bit 7 in Register 0Fh.)

15H

W/R

7:0

Test Register

Reserved for future use.

16H

W/R

7:0

Test Register

Reserved for future use.

17H

7:0

Test Register

Reserved for future use.

18H

7:0

Test Register

Reserved for future use.

NOTE

1The AD9886 only updates the PLL divide ratio when the LSBs are written to (Register 02h).

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