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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9886/PCB датащи(PDF) 15 Page - Analog Devices |
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AD9886/PCB датащи(HTML) 15 Page - Analog Devices |
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15 / 32 page  REV. 0 AD9886 –15– O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 Figure 14. Even Pixels from Frame 2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 Figure 15. Combine Frame Output from Graphics Controller O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 Figure 16. Subsequent Frame from Controller Timing (Analog Interface) The following timing diagrams show the operation of the AD9886 analog interface in all clock modes. The part estab- lishes timing by having the sample that corresponds to the pixel digitized when the leading edge of HSYNC occurs sent to the “A” data port. In Dual Channel Mode, the next sample is sent to the “B” port. Future samples are alternated between the “A” and “B” data ports. In Single Channel Mode, data is only sent to the “A” data port, and the “B” port is placed in a high impedance state. The Output Data Clock signal is created so that its rising edge always occurs between “A” data transitions, and can be used to latch the output data externally. There is a pipeline in the AD9886, which must be flushed before valid data becomes available. In all single channel modes, four data sets are presented before valid data is available. In all dual channel modes, two data sets are presented before valid “A” port data is available. tPER tCYCLE tSKEW DATACK DATACK\ DATA HSOUT Figure 17. Output Timing Hsync Timing Horizontal sync is processed in the AD9886 to eliminate ambiguity in the timing of the leading edge with respect to the phase-delayed pixel clock and data. The Hsync input is used as a reference to generate the pixel sampling clock. The sampling phase can be adjusted, with respect to Hsync, through a full 360 ° in 32 steps via the Phase Adjust register (to optimize the pixel sampling time). Display systems use Hsync to align memory and display write cycles, so it is important to have a stable timing relationship between Hsync output (HSOUT) and data clock (DATACK). Three things happen to Horizontal Sync in the AD9886. First, the polarity of Hsync input is determined and will thus have a known output polarity. The known output polarity can be pro- grammed either active high or active low (Register 04H, Bit 4). Second, HSOUT is aligned with DATACK and data outputs. Third, the duration of HSOUT (in pixel clocks) is set via Regis- ter 07H. HSOUT is the sync signal that should be used to drive the rest of the display system. Coast Timing In most computer systems, the Hsync signal is provided con- tinuously on a dedicated wire. In these systems, the COAST input and function are unnecessary, and should not be used. In some systems, however, Hsync is disturbed during the Verti- cal Sync period (Vsync). In some cases, Hsync pulses disappear. In other systems, such as those that employ Composite Sync (Csync) signals or embed Sync-On-Green (SOG), Hsync includes equalization pulses or other distortions during Vsync. To avoid upsetting the clock generator during Vsync, it is important to ignore these distortions. If the pixel clock PLL sees extraneous pulses, it will attempt to lock to this new frequency, and will have changed frequency by the end of the Vsync period. It will then take a few lines of correct Hsync timing to recover at the beginning of a new frame, resulting in a “tearing” of the image at the top of the display. The COAST input is provided to eliminate this problem. It is an asynchronous input that disables the PLL input and allows the clock to free-run at its then-current frequency. The PLL can free-run for several lines without significant frequency drift. |
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