AD9886SLASHPCB datasheet(26/32 Pages) AD

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AD9886

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SYNC DETECTION AND CONTROL

Analog Interface HSYNC Detect

This bit is used to indicate when activity is detected on

the HSYNC input pin (Pin 82). If HSYNC is held high or

low, activity will not be detected.

Table XXVI. HSYNC Detection Results

Detect

Function

No Activity Detected

Activity Detected

Figure 38 shows where this function is implemented.

Analog Interface Sync-on-Green Detect

This bit is used to indicate when sync activity is detected

on the Sync-on-Green input pin (Pin 108).

Table XXVII. Sync-on-Green Detection Results

Detect

Function

No Activity Detected

Activity Detected

Figure 38 shows where this function is implemented.

Warning: If no sync is present on the green video input,

normal video may still trigger activity.

Analog Interface VSYNC Detect

This bit is used to indicate when activity is detected on

the VSYNC input pin (Pin 81). If VSYNC is held high or

low, activity will not be detected.

Table XXVIII. VSYNC Detection Results

Detect

Function

No Activity Detected

Activity Detected

Figure 38 shows where this function is implemented.

Digital Interface Clock Detect

This bit is used to indicate when activity is detected on

the digital interface clock input.

Table XXIX. Digital Interface Clock Detection Results

Detect

Function

No Activity Detected

Activity Detected

The sync processing block diagram shows where this

function is implemented.

Active Interface

This bit is used to indicate which interface should be

active, analog or digital. It checks for activity on the

analog interface and for activity on the digital interface,

then determines which should be active according to

Table XXX. Specifically, analog interface detection is

determined by OR-ing Bits 7, 6, and 5 in this register.

Digital interface detection is determined by Bit 4 in this

determine which has priority via Bit 6 in register 12H.

The user can override this function via Bit 7 in Register

12H. If the override bit is set to Logic 1, then this bit will

be forced to whatever the state of Bit 6 in Register 12H is

set to.

Table XXX. Active Interface Results

Bits 7, 6,

or 5

Bit 4

(Analog

(Digital

Detection)

Override

Soft

Power-Down

(Seek Mode)

010

100

Bit 6 in 12H

AI = 0 means Analog Interface.

AI = 1 means Digital Interface.

The override bit is in Register 12H, Bit 7.

AHS—Active HSYNC

This bit is used to determine which HSYNC should be

used for the analog interface, the HSYNC input or Sync-

on-Green. It uses Bits 7 and 6 in this register for inputs

in determining which should be active. Similar to the previ-

ous bit, if both HSYNC and SOG are detected the user

can determine which has priority via Bit 4 in Register

12H. The user can override this function via Bit 5 in

bit will be forced to whatever the state of Bit 4 in Register

12H is set to.

Table XXXI. Active HSYNC Results

Bit 7

Bit 6

(HSYNC

(SOG

Detect)

Override

AHS

Bit 4 in 12H

101

000

Bit 4 in 12H

AHS = 0 means use the HSYNC pin input for HSYNC.

AHS = 1 means use the SOG pin input for HSYNC.

The override bit is in Register 12H, Bit 5.

AVS—Active VSYNC

This bit is used to determine which VSYNC should be

used for the analog interface; the VSYNC input or output

from the sync separator. It uses Bit 5 in this register as the

input for determining which should be active. Similar to

the previous bit, if both HSYNC and SOG are detected

the user can determine which has priority via Bit 4 in

in Register 12H. If the override bit is set to Logic 1, this

bit will be forced to whatever the state of Bit 2 in Register

12H is set to.

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