AD9886SLASHPCB datasheet(12/32 Pages) AD

12 / 32 page

REV. 0

AD9886

–12–

Sync-on-Green

The Sync-on-Green input operates in two steps. First, it sets a

baseline clamp level from the incoming video signal with a

negative peak detector. Second, it sets the sync trigger level to

~150 mV above the negative peak. The Sync-on-Green input

must be ac-coupled to the green analog input through its own

capacitor as shown in Figure 4. The value of the capacitor must

be 1 nF

±20%. If Sync-on-Green is not used, this connection is

not required. (Note: The Sync-on-Green signal is always nega-

tive polarity.)

RAIN

BAIN

GAIN

SOG

47nF

1nF

Figure 4. Typical Clamp Configuration for RGB/YUV

Applications

Clock Generation

A Phase Locked Loop (PLL) is employed to generate the pixel

clock. In this PLL, the Hsync input provides a reference fre-

quency. A Voltage Controlled Oscillator (VCO) generates a

much higher pixel clock frequency. This pixel clock is divided

by the PLL divide value (Registers 01H and 02H) and phase

compared with the Hsync input. Any error is used to shift the

VCO frequency and maintain lock between the two signals.

The stability of this clock is a very important element in provid-

ing the clearest and most stable image. During each pixel time,

there is a period during which the signal is slewing from the old

pixel amplitude and settling at its new value. Then there is a

time when the input voltage is stable, before the signal must

slew to a new value (see Figure 5). The ratio of the slewing time

to the stable time is a function of the bandwidth of the graphics

DAC and the bandwidth of the transmission system (cable and

termination). It is also a function of the overall pixel rate. Clearly,

if the dynamic characteristics of the system remain fixed, the

slewing and settling time is likewise fixed. This time must be

subtracted from the total pixel period, leaving the stable period.

At higher pixel frequencies, the total cycle time is shorter, and

the stable pixel time becomes shorter as well.

PIXEL CLOCK

INVALID SAMPLE TIMES

Figure 5. Pixel Sampling Times

Any jitter in the clock reduces the precision with which the

sampling time can be determined, and must also be subtracted

from the stable pixel time.

Considerable care has been taken in the design of the AD9886’s

clock generation circuit to minimize jitter. As indicated in Fig-

ure 6, the clock jitter of the AD9886 is less than 5% of the total

pixel time in all operating modes, making the reduction in the

valid sampling time due to jitter negligible.

FREQUENCY – MHz

31.5

36.0 36.0 50.0 56.25 44.9 75.0 85.5

135.0

Figure 6. Pixel Clock Jitter vs. Frequency

The PLL characteristics are determined by the loop filter

design, by the PLL charge pump current and by the VCO range

setting. The loop filter design is illustrated in Figure 7. Recom-

mended settings of VCO range and charge pump current for

VESA standard display modes are listed in Table IV.

CP0.0039 F

0.039 F CZ

3.3k

FILT

PVD

Figure 7. PLL Loop Filter Detail

Four programmable registers are provided to optimize the per-

formance of the PLL. These registers are:

1. The 12-Bit Divisor Register. The input Hsync frequencies

range from 15 kHz to 110 kHz. The PLL multiplies the

frequency of the Hsync signal, producing pixel clock fre-

quencies in the range of 12 MHz to 140 MHz. The Divisor

may be set to any value between 221 and 4095. (The divide

ratio that is actually used is the programmed divide ratio

plus one.)

2. The 2-Bit VCO Range Register. To lower the sensitivity of

the output frequency to noise on the control signal, the VCO

operating frequency range is divided into four overlapping

regions. The VCO Range register sets this operating range.

Because there are only four possible regions, only the two

least-significant bits of the VCO Range register are used.

The frequency ranges for the lowest and highest regions

are shown in Table II.

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