AD9886SLASHPCB datasheet(11/32 Pages) AD

11 / 32 page

REV. 0

AD9886

–11–

The clamp timing can be established by simply exercising the

CLAMP pin at the appropriate time (with EXTCLMP = 1).

The polarity of this signal is set by the Clamp Polarity bit.

A simpler method of clamp timing employs the AD9886 inter-

nal clamp timing generator. The Clamp Placement register is

programmed with the number of pixel times that should pass

after the trailing edge of HSYNC before clamping starts. A

second register (Clamp Duration) sets the duration of the

clamp. These are both 8-bit values, providing considerable

flexibility in clamp generation. The clamp timing is referenced

to the trailing edge of HSYNC because, although HSYNC

duration can vary widely, the back porch (black reference)

always follows HSYNC. A good starting point for establishing

clamping is to set the clamp placement to 08h (providing eight

pixel periods for the graphics signal to stabilize after sync) and

set the clamp duration to 14h (giving the clamp 20 pixel periods

to reestablish the black reference).

Clamping is accomplished by placing an appropriate charge on

the external input coupling capacitor. The value of this capaci-

tor affects the performance of the clamp. If it is too small, there

will be a significant amplitude change during a horizontal line

time (between clamping intervals). If the capacitor is too large,

it will take excessively long for the clamp to recover from a large

change in incoming signal offset. The recommended value

(47 nF) results in recovering from a step error of 100 mV to

within 1/2 LSB in 10 lines with a clamp duration of 20 pixel

periods on a 60 Hz SXGA signal.

YUV Clamping

YUV graphic signals are slightly different from RGB signals in

that the dc reference level (black level in RGB signals) can be at

the midpoint of the video signal rather than the bottom. For

these signals it can be necessary to clamp to the midscale range

of the A/D converter range (10h) rather than bottom of the A/D

converter range (00h).

Clamping to midscale rather than ground can be accomplished

by setting the clamp select bits in the series bus register. Each of

the three converters has its own selection bit so that they can be

clamped to either midscale or ground independently. These bits

are located in Register 0Fh and are Bits 0–2.

The midscale reference voltage that each A/D converter clamps

to is provided independently on the RMIDSCV, GMIDSCV, and

BMIDSCV pins. Each converter must have its own midscale refer-

ence because both offset adjustment and gain adjustment for

each converter will affect the dc level of midscale.

During clamping, each A/D converter is clamped to its respec-

tive midscale reference input. These inputs are pins RCLAMPV,

GCLAMPV, and BCLAMPV for the red, green, and blue converters

respectively. The typical connections for both RGB and YUV

clamping are shown below in Figure 2. Note: if midscale clamp-

ing is not required, all of the midscale voltage outputs should

still be connected to ground through a 0.1

µF capacitor.

RMIDSCV

RCLAMPV

GMIDSCV

GCLAMPV

BMIDSCV

BCLAMPV

0.1 F

Figure 2. Typical Clamp Configuration for RBG/YUV

Applications

Gain and Offset Control

The AD9886 can accommodate input signals with inputs rang-

ing from 0.5 V to 1.0 V full scale. The full-scale range is set in

three 8-bit registers (Red Gain, Green Gain, and Blue Gain).

Note that increasing the gain setting results in an image with

less contrast.

The offset control shifts the entire input range, resulting in a

change in image brightness. Three 7-bit registers (Red Offset,

Green Offset, Blue Offset) provide independent settings for

each channel.

The offset controls provide a

±63 LSB adjustment range. This

range is connected with the full-scale range, so if the input range

is doubled (from 0.5 V to 1.0 V) then the offset step size is also

doubled (from 2 mV per step to 4 mV per step).

Figure 3 illustrates the interaction of gain and offset controls.

The magnitude of an LSB in offset adjustment is proportional

to the full-scale range, so changing the full-scale range also

changes the offset. The change is minimal if the offset setting is

near midscale. When changing the offset, the full-scale range is

not affected, but the full-scale level is shifted by the same amount

as the zero-scale level.

GAIN

1.0V

0.0V

00h

FFh

0.5V

OFFSET = 00h

OFFSET = 3Fh

OFFSET = 7Fh

OFFSET = 00h

OFFSET = 7Fh

OFFSET = 3Fh

Figure 3. Gain and Offset Control

AD9886/PCB датащи(PDF) 11 Page - Analog Devices

AD9886/PCB датащи(HTML) 11 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

датащи скачать

ссылки URL