AD9886SLASHPCB datasheet(28/32 Pages) AD

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AD9886

–28–

DIGITAL CONTROL

7:0

Sync Separator Threshold

This register is used to set the responsiveness of the sync

separator. It sets how many pixel clock pulses the sync

separator must count to before toggling high or low. It

works like a low-pass filter to ignore Hsync pulses in order

to extract the Vsync signal. This register should be set to

some number greater than the maximum Hsync pulsewidth.

The default for this register is 32.

CONTROL BITS

Scan Enable

This register is used to enable the scan function. When

enabled, data can be loaded into the AD9886 outputs

serially with the scan function. The scan function utilizes

three pins (SCANIN, SCANOUT, and SCANCLK). These

pins are described in Table I.

Table XLI. Scan Enable Settings

Scan Enable

Result

Scan Function Disabled

Scan Function Enabled

The default for scan enable is 0 (disabled).

Coast Input Polarity Override

This register is used to override the internal circuitry that

determines the polarity of the coast signal going into

the PLL.

Table XLII. Coast Input Polarity Override Settings

Override Bit

Result

Coast Polarity Determined by Chip

Coast Polarity Determined by User

The default for coast polarity override is 0 (polarity

determined by chip).

HSYNC Input Polarity Override

This register is used to override the internal circuitry that

determines the polarity of the Hsync signal going into

the PLL.

Table XLIII. HSYNC Input Polarity Override Settings

Override Bit

Result

Hsync Polarity Determined by Chip

Hsync Polarity Determined by User

The default for Hsync polarity override is 0 (polarity

determined by chip).

2-WIRE SERIAL CONTROL PORT

A 2-wire serial interface control interface is provided. Up to four

AD9886 devices may be connected to the 2-wire serial interface,

with each device having a unique address.

The 2-wire serial interface comprises a clock (SCL) and a bidi-

rectional data (SDA) pin. The Analog Flat Panel Interface acts

as a slave for receiving and transmitting data over the serial

interface. When the serial interface is not active, the logic levels

on SCL and SDA are pulled HIGH by external pull-up resistors.

Data received or transmitted on the SDA line must be stable for

the duration of the positive-going SCL pulse. Data on SDA must

change only when SCL is LOW. If SDA changes state while SCL

is HIGH, the serial interface interprets that action as a start or

stop sequence.

There are six components to serial bus operation:

• Start Signal

• Slave Address Byte

• Base Register Address Byte

• Data Byte to Read or Write

• Stop Signal

When the serial interface is inactive (SCL and SDA are HIGH)

communications are initiated by sending a start signal. The start

signal is a HIGH-to-LOW transition on SDA while SCL is

HIGH. This signal alerts all slaved devices that a data transfer

sequence is coming.

The first eight bits of data transferred after a start signal com-

prising a 7-bit slave address (the first seven bits) and a single R/

bit (the eighth bit). The R/

W bit indicates the direction of data

transfer, read from (1) or write to (0) the slave device. If the

transmitted slave address matches the address of the device (set

by the state of the SA1-0 input pins in Table XLIV, the AD9886

acknowledges by bringing SDA LOW on the 9th SCL pulse. If

the addresses do not match, the AD9886 does not acknowledge.

Table XLIV. Serial Port Addresses

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(MSB)

01100

01101

01110

01111

Data Transfer via Serial Interface

For each byte of data read or written, the MSB is the first bit of

the sequence.

If the AD9886 does not acknowledge the master device during a

write sequence, the SDA remains HIGH so the master can

generate a stop signal. If the master device does not acknowledge

the AD9886 during a read sequence, the AD9886 interprets this

as “end of data.” The SDA remains HIGH so the master can

generate a stop signal.

Writing data to specific control registers of the AD9886 requires

that the 8-bit address of the control register of interest be written

after the slave address has been established. This control register

address is the base address for subsequent write operations. The

base address autoincrements by one for each byte of data written

after the data byte intended for the base address. If more bytes

are transferred than there are available addresses, the address will

not increment and remain at its maximum value of 1Dh. Any base

address higher than 1Dh will not produce an acknowledge signal.

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