STM32F303C6 datasheet(16/115 Pages) STMICROELECTRONICS

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Functional overview

STM32F303x6/x8

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DocID025083 Rev 5

3.5

Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous

communication between peripherals, saving CPU resources thus power supply

consumption. In addition, these hardware connections allow fast and predictable latency.

Note:

For more details about the interconnect actions, refer to the corresponding sections in the

RM0364 reference manual.

3.6

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example with

failure of an indirectly used external oscillator).

Several prescalers allow to configure the AHB frequency, the high-speed APB (APB2) and

the low-speed APB (APB1) domains. The maximum frequency of the AHB and the

Table 4. STM32F303x6/8 peripheral interconnect matrix

Interconnect source

Interconnect

destination

Interconnect action

TIMx

Timers synchronization or chaining

ADCx

DACx

Conversion triggers

DMA

Memory to memory transfer trigger

COMPx

Comparator output blanking

COMPx

TIMx

Timer input: ocrefclear input, input capture

ADCx

TIM1

Timer triggered by analog watchdog

GPIO

RTCCLK

HSE/32

MC0

TIM16

Clock source used as input channel for HSI and

LSI calibration

CSS

CPU (hard fault)

RAM (parity error)

COMPx

PVD

GPIO

TIM1

TIM15, 16, 17

Timer break

GPIO

TIMx

External trigger, timer break

ADCx

DACx

Conversion external trigger

DACx

COMPx

Comparator inverting input

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