STM32F303C6 datasheet(15/115 Pages) STMICROELECTRONICS

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DocID025083 Rev 5

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STM32F303x6/x8

Functional overview

remains in reset mode when the monitored supply voltage is below a specified threshold,

VPOR/PDR, without the need for an external reset circuit.

•

The POR monitors only the VDD supply voltage. During the startup phase it is required

that VDDA should arrive first and be greater than or equal to VDD.

•

The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power

supply supervisor can be disabled (by programming a dedicated Option bit) to reduce

the power consumption if the application design ensures that VDDA is higher than or

equal to VDD.

The device features an embedded programmable voltage detector (PVD) that monitors the

VDD power supply and compares it to the VPVD threshold. An interrupt can be generated

when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD

threshold. The interrupt service routine can then generate a warning message and/or put

the MCU into a safe state. The PVD is enabled by software.

3.4.3

Voltage regulator

The regulator has three operation modes: main (MR), low-power (LPR), and power-down.

•

The MR mode is used in the nominal regulation mode (Run)

•

The LPR mode is used in Stop mode.

•

The power-down mode is used in Standby mode: the regulator output is in high

impedance, and the kernel circuitry is powered down thus inducing zero consumption.

The voltage regulator is always enabled after reset. It is disabled in Standby mode.

3.4.4

Low-power modes

The STM32F303x6/8 supports three low-power modes to achieve the best compromise

between low power consumption, short startup time and available wakeup sources:

•

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

•

Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output, the RTC alarm, COMPx,

I2C or USARTx.

•

Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note:

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

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