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STM32F303C6 датащи(PDF) 13 Page - STMicroelectronics |
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STM32F303C6 датащи(HTML) 13 Page - STMicroelectronics |
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13 / 115 page ![]() DocID025083 Rev 5 13/115 STM32F303x6/x8 Functional overview 43 3 Functional overview 3.1 ARM® Cortex®-M4 core with FPU with embedded Flash and SRAM The ARM Cortex-M4 processor with FPU is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM 32-bit Cortex-M4 RISC processor with FPU features exceptional code-efficiency, delivering the high performance expected from an ARM core, with memory sizes usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allows efficient signal processing and complex algorithm execution. Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation. With its embedded ARM core, the STM32F303x6/8 family is compatible with all ARM tools and software. Figure 1 shows the general block diagram of the STM32F303x6/8 family devices. 3.2 Memories 3.2.1 Embedded Flash memory All STM32F303x6/8 devices feature up to 64 Kbytes of embedded Flash memory available for storing programs and data. The Flash memory access time is adjusted to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above). 3.2.2 Embedded SRAM The STM32F303x6/8 devices feature 12 Kbytes of embedded SRAM with hardware parity check. The memory can be accessed in read/write at CPU clock speed with 0 wait states, allowing the CPU to achieve 90 Dhrystone Mips at 72 MHz when running code from CCM (core coupled memory) RAM. The SRAM is organized as follows: • 4 Kbytes of SRAM on instruction and data bus with parity check (core coupled memory or CCM) and used to execute critical routines or to access data • 12 Kbytes of SRAM with parity check mapped on the data bus. |
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