ESE

SEMICONDUCTOR CORPORATION

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC7212

Gigabit Interconnect Chip

Page 4

G52268-0, Rev 3.3

04/10/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

A similar situation exists when TBC is used to define a data eye; only the rising edges of TBC are used to

define the external data timing. The internal clock active edges are placed at 90× and 270× points between

consecutive TBC rising edges (which are assumed to be 360× apart).

Figure 2: Transmit Timing, TMODE(2:0) = 000

Figure 3: Transmit Timing, TMODE(2:0) = 10X

Figure 4: Transmit Timing, TMODE(2:0) = 11X (“ASIC-Friendly” Timing)

REFCLK

(DUAL = 0)

Valid

C/D

Valid

Valid

T(7:0)

WSEN

REFCLK

(DUAL = 1)

Valid

C/D

Valid

Valid

T(7:0)

WSEN

TBC

Valid

C/D

Valid

Valid

T(7:0)

WSEN

TBC

0

o

90

o

180

o

270

o

360

o