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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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VSC7212 датащи(PDF) 31 Page - Vitesse Semiconductor Corporation |
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VSC7212 датащи(HTML) 31 Page - Vitesse Semiconductor Corporation |
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31 / 34 page  VITESSE SEMICONDUCTOR CORPORATION VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC7212 Gigabit Interconnect Chip G52268-0, Rev 3.3 Page 31 04/10/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com 29 FLOCK I TTL Frequency LOCKed Mode. When HIGH indicates that the transmitting device’s REFCLK is frequency-locked to the receiver’s word clock. Controls rate matching (IDLE delete/duplicate) logic along with the WSI input as defined in Table 6. 27 BIST I TTL Built-In Self Test Mode. When HIGH, the transmitter continuously sends a 256 byte incrementing data pattern, and the receiver signals correct reception of the test pattern with a LOW on TBERR. 28 ENDEC I TTL ENcoder/DECoder Enable. When HIGH the VSC7212 is configured for 8 bit operation, internal 8B/10B encoding is enabled. When LOW, a 10-bit interface is used and internal 8B/10B encoding is bypassed. 38 RESETN I TTL RESETN Input. When asserted LOW, the transmitter input skew buffer and receiver elastic buffer are recentered. 39 WSI I TTL Word Sync Input. Used to control chip-to-chip alignment and IDLE character insertion/deletion as defined in Table 6. 45 WSO O TTL Word Sync Output. Used to set initial chip-to-chip word alignment, and to maintain alignment by controlling IDLE character insertion/deletion. 79 TCK I TTL JTAG Test Access Port Test Clock Input 78 TMS I TTL JTAG Test Access Port Test Mode Select Input 77 TDI I TTL JTAG Test Access Port Test Data Input 74 TDO O TTL JTAG Test Access Port Test Data Output 80 TRSTN I TTL JTAG Test Access Port Test Logic Reset Input 40 41 RSVD0 RSVD1 I N/A Reserved Inputs for future use. Set HIGH for compatibility reasons. 12 VDDA P VDD Analog power supply to PLL. 15 VSSA P GND Analog ground to PLL. 16,24,32 42,84,94 VDDD P VDD Digital power supply. 6,11,19,33 44,83,93 VSSD P GND Digital ground. 49,57,64 70 VDDT P VDD TTL output power supply. 47,54,59 62,67,72 VSST P GND TTL output ground. 3 8 VDDP VDDR P VDD PECL Output power supply for PTX. PECL Output power supply for RTX. If use of an output is not necessary, leave the power supply pin open. 1,25,26 50,51,75 76,100 N/C Not connected internally. Pin Name I/O Type Pin Description |
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