VITESSE

SEMICONDUCTOR CORPORATION

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC7212

Gigabit Interconnect Chip

G52268-0, Rev 3.3

Page 1

04/10/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Features

General Description

The VSC7212 is an 8-bit parallel-to-serial and serial-to-parallel transceiver chip used for high bandwidth

interconnection between busses, backplanes, or other subsystems. A Fibre Channel and Gigabit Ethernet

compliant transceiver provides up to 2.18Gb/s of duplex raw data transfer. The VSC7212 can operate at a

maximum data transfer rate of 1088Mb/s (8 bits at 136MHz) or a minimum rate of 784Mb/s (8 bits at 98MHz).

The VSC7212 contains an 8B/10B encoder, serializer, de-serializer, 8B/10B decoder and elastic buffer which

provide the user with a simple interface for transferring data serially and recovering it on the receive side. The

device can also be configured to operate as a non-encoded 10-bit transceiver with redundant I/O.

VSC7212 Block Diagram

• ANSI X3T11 Compliant Fibre Channel and IEEE

802.3z Compliant Gigabit Ethernet Transceiver

• Over 2Gb/s Duplex Raw Data Rate

• Redundant PECL Tx Outputs and Rx Inputs

• 8B/10B Encoder/Decoder, Optional Encoder/

Decoder Bypass Operation

ter Parallel Input Data

• Elastic Buffer for Chip-to-Chip Cable Deskewing

• Tx/Rx Rate Matching via IDLE Insertion/Deletion

• Compatible with VSC7211, VSC7214 and

VSC7216

• Received Data Aligned to Local REFCLK or to

Recovered Clock

• PECL Rx Signal Detect and Cable Equalization

• Serial Tx-to-Rx and Parallel Rx-to-Tx Internal

Loopback Modes

• Clock Multiplier Generates Baud Rate Clock

• Automatic Lock-to-Reference

• JTAG Boundary Scan Support for TTL I/O

• Built-In Self Test

• 3.3V Supply, 1.0 W

• 100-pin, 14mm TQFP package

x20/x10

Clock Gen

Tx Clock

ENDEC

RESETN

WSI

DUAL

Channel

Align

WSO

TBC

KCHAR

10

Encode

8B/10B

DQ

T(7:0)

C/D

88

PTX-

PTX+

RTX-

RTX+

WSEN

RTXEN

PTXEN

PRX-

PRX+

RRX-

RRX+

RXP/R

LBEN(1:0)

Recovery

Clk/Data

Decode

8B/10B

10

Buffer

Elastic

3

8

IDLE

ERR

R(7:0)

KCH

8

RCLKN

RCLK

REFCLKP

REFCLKN

REFCLK

TBERR

TMODE(2:0)

FLOCK

TMS

TRSTN

TDI

TCK

TDO

Boundary

JTAG

Scan

RMODE(1:0)

CAP0 CAP1

TRANSMITTER

RECEIVER

BIST

LBTX

RSDET

PSDET

REFOUT