поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

VSC7212 датащи(PDF) 20 Page - Vitesse Semiconductor Corporation

номер детали VSC7212
подробное описание детали  Gigabit Interconnect Chip
PDF  34 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  VITESSE [Vitesse Semiconductor Corporation]
домашняя страница  http://www.vitesse.com
Logo VITESSE - Vitesse Semiconductor Corporation

VSC7212 датащи(HTML) 20 Page - Vitesse Semiconductor Corporation

Back Button VSC7212 Datasheet HTML 16Page - Vitesse Semiconductor Corporation VSC7212 Datasheet HTML 17Page - Vitesse Semiconductor Corporation VSC7212 Datasheet HTML 18Page - Vitesse Semiconductor Corporation VSC7212 Datasheet HTML 19Page - Vitesse Semiconductor Corporation VSC7212 Datasheet HTML 20Page - Vitesse Semiconductor Corporation VSC7212 Datasheet HTML 21Page - Vitesse Semiconductor Corporation VSC7212 Datasheet HTML 22Page - Vitesse Semiconductor Corporation VSC7212 Datasheet HTML 23Page - Vitesse Semiconductor Corporation VSC7212 Datasheet HTML 24Page - Vitesse Semiconductor Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 20 / 34 page
background image
ESE
SEMICONDUCTOR CORPORATION
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
Page 20
G52268-0, Rev 3.3
04/10/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
AC Characteristics
Figure 13: Transmit Input Timing Waveforms with TMODE = 000
Figure 14: Transmit Input Timing Waveforms with TMODE = 10X
Table 9: Transmit Input AC Characteristics with TMODE = 000 or TMODE = 10X
Parameters
Description
Min
Max
Units
Conditions
T1
Input Setup time to the rising
edge of REFCLK or TBC
1.5
ns
Measured between the valid data
level of the input and the 1.4V point
of REFCLK or TBC
T2
Input Hold time after the rising
edge of REFCLK or TBC
1.0
ns
Valid
T1
T2
REFCLK
Valid
Valid
T1
T2
Internal Clock
(from PLL)
(DUAL=1)
REFCLK
(DUAL=0)
T(7:0)
C/D
WSEN
Valid
T1
T2
Valid
Valid
T1
T2
Internal Clock
(from PLL)
TBC
T(7:0)
C/D
WSEN



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com