ESE

SEMICONDUCTOR CORPORATION

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC7212

Gigabit Interconnect Chip

Page 2

G52268-0, Rev 3.3

04/10/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Notation

Differential signals (i.e., PTX+ and PTX-) may be referred to as a single signal (i.e., PTX) by dropping

reference to the “+” and “- ”. REFCLK refers to the single-ended TTL or differential PECL input pair

REFCLKP/REFCLKN, whichever is used.

Clock Synthesizer

Depending on the state of the DUAL input, the VSC7212 clock synthesizer multiplies the reference

frequency provided on the REFCLK input by 10 (DUAL is LOW) or 20 (DUAL is HIGH) to achieve a baud

rate clock between 0.98GHz and 1.36GHz. The on-chip PLL uses a single external 0.1µF capacitor, connected

between CAP0 and CAP1, to control the Loop Filter. This capacitor should be a multilayer ceramic dielectric,

or better, with at least a 5V working voltage rating and a good temperature coefficient; NPO is preferred but

X7R may be acceptable. These capacitors are used to minimize the impact of common-mode noise on the Clock

Multiplier Unit, especially power supply noise. Higher value capacitors provide better robustness in systems.

NPO is preferred because if an X7R capacitor is used, the power supply noise sensitivity will vary with

temperature. For best noise immunity, the designer may use a three capacitor circuit with one differential

capacitor between CAP0 and CAP1, C1, a capacitor from CAP0 to ground, C2, and a capacitor from CAP1 to

ground, C3. Larger values are better but 0.1µF is adequate. However, if the designer cannot use a three capacitor

circuit, a single differential capacitor, C1, is adequate. These components should be isolated from noisy traces.

Figure 1: Loop Filter Capacitors (Best Circuit)

The REFCLK signal can be either single-ended TTL or differential LVPECL. If TTL, connect the TTL

input to REFCLKP but leave REFCLKN open. If LVPECL, connect the inputs to REFCLKP and REFCLKN.

CAP0

CAP1

C1

C2

C3

VSC7216

C1=C2=C3= >0.1µF

MultiLayer Ceramic

Surface Mount

NPO (Preferred) or X7R

5V Working Voltage Rating