ESE

SEMICONDUCTOR CORPORATION

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC7212

Gigabit Interconnect Chip

Page 10

G52268-0, Rev 3.3

04/10/01

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of the VSC7212 only on the rising edge of the selected word clock at 1/10th the baud rate. Timing waveforms

for the output data and status are shown in Figure 6, Figure 7 and Figure 8.

Figure 6: Receive Timing, RMODE(1:0) = 00

Figure 7: Receive Timing, RMODE(1:0) = 01

Figure 8: Receive Timing, RMODE(1:0) = 1X

REFCLK

(DUAL = 0)

Valid

IDLE

Valid

Valid

R(7:0)

KCH

REFCLK

(DUAL = 1)

ERR

REFCLK

(DUAL = 0)

IDLE

Valid

Valid

R(7:0)

KCH

REFCLK

(DUAL = 1)

ERR

Valid

RCLK

(DUAL = 0)

Valid

IDLE

Valid

Valid

R(7:0)

KCH

RCLK

(DUAL = 1)

ERR