PC87570-ICCSLASHVUL datasheet(126/168 Pages) NSC

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Analog to Digital Converter (ADC) - January 1998

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16.5.3

Filtering the Noise on Input Signals

Input signals may be accompanied by unwanted noises

caused by the digital circuits they pass nearby. Optionally,

when converting slow changing signals in a noisy environ-

ment, a low pass filter (LPF) may be added externally. This

can be implemented simply by placing a low value capaci-

tor, C1, on the divider output shown in Figure 16-2. The cut-

off frequency of this LPF should be above the measured

signal frequency.

16.5.4

AD0-7 Multiplexing with PD0-7 Port

Analog input signals AD0-7 are multiplexed with digital input

signals PD0-7. These pins do not have internal pull-up re-

sistors and back-drive protection (see Section 16.5.1 on

page 125 for futher details).

Each pin function is selected by dedicated bits in the PDALT

the pins is between zero and the actual VCC/AVCC, the cur-

rent consumption is kept to a minimum, as follows:

Pins used as digital inputs (PD0-7, PDALT=00h):

If the CR16A core is not reading from the PDDIN Reg-

ister or the chip is in Idle mode, the input buffers of

port D are blocked.

Pins used as analog inputs, (AD0-7, PDALT=FFh):

If the chip is either in Active or Idle mode, the input im-

pedance of the pins is as deﬁned in Table 19-5 on

page 134.

For ESD protection reasons, it is not recommended to leave

these pins open. See Table 19-3 on page 133 for their char-

acteristics.

16.5.5

Calculating the Sampling Time

The sampling time is the period between input selection in

the multiplexer and the conversion start (i.e., hold point).

Figure 16-5 shows the schematic of the input and its equiv-

alent R-C circuit. The sampling time should be long enough

to guarantee the settling of the voltage on the sampling ca-

pacitor, CS. The voltage on CS should be stable before it is

held for the duration of the conversion. The RAIN and CAIN

(see Section 19.3.1 on page 134) values represent the input

path serial resistance and parallel capacitance. RAIN is the

serial resistance of the multiplexer, Sample and Hold switch

and other parasitic resistors. CAIN is the parallel capaci-

tance of the input pin, pad, lead-frame, CS, etc. The re-

quired sampling time is determined by RAIN and CAIN

together with the input source resistance RSOURCE and par-

asitic capacitance CP. Table 16-7 can be used as a refer-

ence for calculating the sample time. The DELAY bit of the

ADCCNT3 Register should be programmed accordingly.

Table 16-7. Recommended Sampling Time

External

Elements

Sampling

Time [ns]

Number of ADC Clock Cycles

(min) as function of ADC Clock

(DELAY of ADCCNT3)

[pF]

Ω]

1 MHz

(1000 ns)

500 KHz

(500 ns)

250 KHz

(250 ns)

0.1

110

900

3200

27.5

0.1

210

2220

7900

0.1

430

3350

11400

RAIN

CAIN

Input

Signal

Figure 16-5. Analog Input Schematic Diagram

and Equivalent R-C Circuit

Sample

8:1

Analog

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

MUX

and Hold

VIN

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