PC87570-ICCSLASHVUL datasheet(97/168 Pages) NSC

97 / 168 page

PS/2 Interface

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Bit 0 - Start of Transaction Interrupt Enable (SOTIE)

This bit is used for enabling the interrupt generation on

a transaction start detection. When set (1), the interrupt

signal (PSINT1) to the ICU is active (1) whenever the

PSTAT.SOT bit is set. When SOT is cleared (0), the

PSSTAT.SOT bit does not affect the interrupt signal.

Once set, SOT is not cleared until the shift mechanism

is reset. Therefore SOTIE should be cleared on the first

occurrence of an SOT interrupt. SOTIE should be set (1)

when the PS/2 module is programmed to handle the im-

pending transfer.

Bit 1 - End of Transaction Interrupt Enable (EOTIE)

This bit is used for enabling the interrupt generation on

an End of Transaction detection. When set (1), the inter-

rupt signal (PSINT1) to the ICU is active (1) whenever

the PSTAT.EOT bit is set. When EOTIE is cleared (0),

the PSSTAT.EOT bit does not affect the interrupt signal.

Once set, EOT is not cleared until the shift mechanism

is reset. Therefore EOTIE should be cleared on the first

occurrence of an EOT interrupt. EOTIE should be set (1)

when the PS/2 module is programmed to handle the im-

pending transfer.

Bit 2 - Disabled Shift Mechanism Interrupt Enable (DSMIE)

This bit is used for enabling the interrupt generation

when the shift mechanism is disabled. When set (1), the

clock input signals are connected to the Interrupt Con-

trol Unit (ICU), to allow implementing an interrupt driven

PS/2 protocol. The three interrupts generated are

PSINT1, PSINT2 and PSINT3, for channels 1, 2 and 3,

respectively. When cleared (0), the three interrupt sig-

nals are low. Note that PSINT1 may be activated (1) by

other interrupt sources of the module.

When the shift mechanism is disabled, no debounce is

applied to the PSCLK inputs before producing the inter-

rupt signals, except for local synchronization.

PC87570-ICC/VUL датащи(PDF) 97 Page - National Semiconductor (TI)