PC87570-ICCSLASHVUL datasheet(89/168 Pages) NSC

89 / 168 page

General Purpose I/O (GPIO) Ports

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11.3 GPIO PORT REGISTERS

11.3.1

Port Alternate Function Register (PxALT)

The PxALT Register is a byte-wide, read/write register. It de-

termines if the port will be used as a GPIO port or in its alter-

nate function.

When cleared (0), each bit defines the corresponding pin to

serve as a GPIO signal. The output buffer is controlled by

the Direction and Data Output registers. The input buffer is

routed to the Data In Register. In this case, the input buffer

is blocked, except when the buffer is actually being read

When set (1), each bit defines the pin as its alternate func-

tion. The output buffer data and TRI-STATE are controlled

by signals coming from the alternate module. The input buff-

er is always enabled. The pull-up is enabled when both the

PxWPU is set and the alternate function is either input or bi-

directional.

This register is cleared on reset, setting the pins to GPIO

signals.

11.3.2

Port Direction Register (PxDIR)

The PxDIR Register is a byte-wide, read/write register that

configures pin direction.

When cleared (0), each bit defines the corresponding pin to

serve as an input, placing the output buffer in TRI-STATE.

When set (1), each bit defines the pin as an output, enabling

the output buffer.

On reset, PxDIR is cleared (0). This configures all the pins

in port Px as input.

11.3.3

Port Data Out Register (PxDOUT)

The PxDOUT Register is a byte-wide, read/write register. It

holds the data to be driven onto the pin, when the respective

pin is configured as GPIO and its direction is set as output.

Writing this register sets the values of the output pins.

Reading from it returns the last value written to the register.

11.3.4

Port Data In Register (PxDIN)

The PxDIN Register is a byte-wide, read-only register.

Reading from it returns the current value of the port

pins.This register can always be read.

11.3.5

Port Weak Pull-up Register (PxWPU)

The PxWPU Register is a byte-wide, read/write register,

controlling the pin pull-up. The pull-up is enabled when the

corresponding bit of PxWPU is set and the port buffer is in

TRI-STATE. Otherwise, the pull-up is disabled (i.e., high im-

pedance).

When the pin is configured as an input port, this pull-up can

be used to prevent the input from being in an undefined

state. When the pin is configured as an output port, this pull-

up is disabled.

In both GPIO or alternate function, the pin pull-up function

is enabled by PxWPU.

On reset, PxWPU is cleared (0), disabling all pull-ups.

Px Pins Alternate Function Enable

Px Port Direction

Px Port Output Data

Px Port Input Data

Px Port Weak Pull-up Enable

PC87570-ICC/VUL датащи(PDF) 89 Page - National Semiconductor (TI)

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