PC87570-ICCSLASHVUL datasheet(2/168 Pages) NSC

2 / 168 page

Highlights

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Features

• CR16A Core

— 16-bit embedded RISC processor core

• Bus Interface Unit (BIU)

— Three address zones for static devices (SRAM,

ROM FLASH, I/O)

— Conﬁgurable wait states and fast read bus cycles

• Internal Memory

— 2048 bytes of on-chip ROM

— 1024 bytes of on-chip RAM

— All memories can hold both code and data

• External Memory

— Supports BIOS memory (Flash) sharing with PC host

— Up to 56 Kbyte for code and data

— Field upgradable with Flash or SRAM devices

— Supports host controlled code download and update

• Host Bus Interface (HBI)

— Three host interface channels, typically used for the

KBC, PM and RTC devices

— Motherboard Plug and Play (PnP) conﬁguration

With Enable and Lock bits for each device

Relocatable address for each device

— Host power supply indicator input pin

— 8042 KBC standard Interface (60h, 64h)

— Intel 80C51SL compatible

— IRQ1 and IRQ12 support

— Fast Gate A20 and Fast host Reset, via ﬁrmware

— PM interface port (62h, 66h)

— PM port IRQ11

• Real-Time Clock (RTC) and Advanced Power Control

(APC)

— RTC

DS1287, MC146818 and PC87911 compatible

242 bytes battery backed-up CMOS RAM

Calendar including century and automatic leap-

year adjustment

Optional daylight saving adjustment

BCD or binary format for timekeeping

Three individually maskable interrupt event

ﬂags: periodic rates from 122

µs to 500 ms; time-

of-day alarm, once per second to once per day

Separate backup battery pin

Double buffer time registers

The CMOS RAM and the RTC registers can be

accessed by the CR16A ﬁrmware

— APC

Alarm wake-up

Hardware wake-up events

Software off events

• HFCG

— On-chip frequency multiplier

— Single 32.786KHz crystal

— Software controlled frequency generation

• PMC

— 3.3 and 5V operation with mixed voltage system

support

— Reduced power consumption capability

— Back-drive protection

— Three power modes, switched by software or hard-

ware:

Active mode operating frequency 4-10MHz

Idle (20

µA)

Power Off - RTC only (0.9

µA typical) from back-

up battery

— Automatic wake-up on system events

• ICU

— 16 maskable interrupt sources

— Four general purpose external interrupt inputs

— Programmable trigger mode (level: high or low,

edge: falling or rising)

— Enable and pending indication for each interrupt

— Non-maskable interrupt input

• MIWU

— Supports up to 24 wake-up or interrupt inputs

— Generates wake-up to PMC

— Generates interrupts to ICU

— Provides user-selectable trigger conditions

• GPIO

— 76 ports

— I/O pins individually conﬁgured as input or output

— Conﬁgurable internal pull-up resistors

— Special ports for internal keyboard matrix scanning

16 open-collector outputs

8 Schmidt inputs with internal pull-up

— Special input for system On/Off switch

— Supports very low-cost implementation of additional

off-chip I/O ports

• PS/2 Interface

— Supports three independent devices (external KBC,

mouse and additional pointing device)

— Supports byte level handling via hardware accelerator

• ACB Interface

— Intel SMBus and Philips I2C® compatible

— ACCESS.bus master and slave

— Supports polling and interrupt controlled operation

— Generates a wake-up signal on detection of a Start

Condition, while in power-down mode

— Optional internal pull-up on SDA and SCL pins

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