PC87570-ICCSLASHVUL datasheet(40/168 Pages) NSC

40 / 168 page

Bus Interface Unit (BIU)

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3.3.5

Normal Read Bus Cycle

A read bus cycle starts at T1, when the address is placed

on the address bus, and SELn (or SELIO) is activated.

WR0-1 are inactive, indicating that this is a read bus cycle.

The RD signal is activated on the first TIW or T2 (when

there are no TIW cycles).

At the end of T2, the BIU samples the data on D0-7 or D0-15,

according to the SZCFGn.BW signal. After T2, the number of

Thold cycles specified by SZCFGn.HOLD (may be 0) are add-

ed. SELn and RD deactivate on the first Thold cycle. The ad-

dress remains valid until the end of the last Thold cycle.

When no Thold cycles are specified, SELn deactivates in the

clock cycle that follows T2, unless another read from the

same zone follows. The RD signal always deactivates in the

clock cycle following T2. See Figures 3-7,3-8 and 3-9.

A burst bus cycle supplements the basic read bus cycle if

the core attempts to access more bytes (i.e., a word) than

the configured bus width (and SZCFGn.BRE is set to 1).

The burst bus cycle (T2B) follows T2, before the Thold cy-

cles (if configured). A wait clock cycle (TBW) is added be-

tween T2 and T2B, if SZCFGn.WBR is set to 1.

The address of the burst bus cycle is changed on TBW (if

configured) or T2B (if no TBW). At the end of T2B, data is

sampled. The RD signal is activated during the burst bus cy-

cle; it deactivates in the clock cycle following T2B. See Fig-

ures 3-10 and 3-11.

CLK

A0:18

SELx

SELy

WR0-1

D(0-15)

Normal Read

TIdle

≠ y)

≠ x)

BST0-2

Figure 3-7. Two Basic Normal Read Bus Cycles with Idle In-between (SZCFGy.IPST = 1, SZCFGx.IPRE =

CLK

A0-18

SELn

D0-15

WR0-1

Bus State

TIW

Thold

BST0-2

Figure 3-8. Normal Read Bus Cycle with 2 Internal Waits and 1 Hold

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