PC87570-ICCSLASHVUL datasheet(56/168 Pages) NSC

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Host Bus Interface (HBI)

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when LKRTCHA in the CST1 Register is set. This register

actually access the Index Register located at host default

address 0070h.

5.12.4

RTC Core Data Register (RTCCD)

The RTCCD Register is a byte-wide, read/write register. A

write to this register writes the RTC Data Register. A read

from this bit reads the RTC Data Register. This register

should be accessed by the PC87570 firmware, only when

LKRTCHA in the CST1 Register is set. This register actually

access the Data Register located at host default address

0071h.

5.12.5

Host PnP Initial Configuration Base Address

Low and High Registers (HCFGBAL/H)

Both HCFGBAL and HCFGBAH are byte-wide, read/write reg-

isters. HCFGBAL holds the least significant byte of a host

motherboard PnP initial configuration address, and HCFG-

BAH holds the most significant byte. The contents of HCFG-

BAH and HCFGBAL do not change during a warm reset

(HMR).

Data written to this register pair can be used to select the

PC87570 during the host motherboard PnP configuration

sequence. Data is considered valid (and is used for address

compare) only when VHCFGA in the CST2 Register is set.

To update the host initial PnP configuration address pro-

ceed as follows:

1. Clear VHCFGA in the CST2 Register.

2. Write the lower byte of the address to HCFGBAL.

3. Write the higher byte of the address to HCFGBAH.

4. After the write to HCFGBAH is completed, the hardware

automatically sets the VHCFGA bit in the CST2 Regis-

ter.

On power-up and WATCHDOG reset, this register is unde-

fined. When HCFGLK in the CST2 Register is set, it locks the

current setting of HCFGBAL and HCFGBAH.

5.12.6

Host Interface Control Register (HICTRL)

The HICTRL Register is a byte wide, read/write register,

used in setting host interface mechanism options. On reset,

non-reserved bits of HICTRL are cleared.

Bit 0 -Output Buffer Full Keyboard Interrupt Enable (OBFKIE)

0: IRQ1 interrupt signal is controlled by IRQ1B bit in

the HIIRQC Register

1: Enables Output Buffer Full interrupt to the keyboard

driver of the host (IRQ1). The interrupt is triggered

by the CR16A write to the HIKDO Register. The in-

terrupt is sent according to IRQM and IRQNPOL

bits in the HIIRQC Register.

Bit 1 - Output Buffer Full Mouse Interrupt Enable (OBFMIE)

0: IRQ12 interrupt signal is controlled by IRQ12B bit in

the HIIRQC Register

1: Enables Output Buffer Full interrupt to the mouse

driver in the host (IRQ12). The interrupt is triggered

by the CR16A write to the HIMDO Register. The in-

terrupt is sent according to IRQM and IRQNPOL

bits in HIIRQC register.

Bit 2 - Output Buffer Empty Core Interrupt Enable (OBECIE)

0: Interrupt signal low

1: Enables Output Buffer Empty interrupt to the

CR16A ICU, for the KBC channel. The interrupt sig-

nal is active when the output buffer is empty (i.e.,

the interrupt signal is set (1) when OBF bit of the

HIKMST Register is cleared).

Bit 3 - Input Buffer Full Core Interrupt Enable (IBFCIE)

0: Interrupt signal low

1: Enables Input Buffer Full interrupt to the CR16A

ICU, for the KBC channel. The interrupt signal is

active when the input buffer is full; the interrupt sig-

nal is set (1) when IBF bit of the HIKMST register is

set.

Bit 4 - PM Host Interrupt Enable (PMHIE)

0: IRQ11 interrupt signal is controlled by IRQ11B bit in

the HIIRQC Register

1: Enables output buffer full interrupt to the PM driver

in the host (IRQ11). The interrupt is triggered by a

CR16A write to the HIPMDO Register. The interrupt is

sent according to IRQM and IRQNPOL in the HIIRQC

Bit 5 - PM Output Buffer Empty Core Interrupt Enable (PMECIE)

0: Interrupt signal low

1: Enables PM output buffer empty interrupt to the

CR16A ICU, for the PM channel. The interrupt signal

is active when the output buffer is empty (when OBF

bit of the HIPMST register is cleared).

Bit 6 - PM Input Buffer Full Core Interrupt Enable (PMICIE)

0: Interrupt signal low

1: Enables PM input buffer full interrupt to the CR16A

ICU, for the PM channel. The interrupt signal is ac-

tive when the input buffer is empty (when IBF bit in

the HIPMST Register is set).

5.12.7

Host Interface IRQ Control Register (HIIRQC)

The HIIRQC Register is a byte wide, read/write register. It

controls the IRQ signals mode of operation. On reset, HI-

IRQC is preset to 07h.

76543210

MSB

RTC Address

LSB

76543210

MSB

RTC Data

LSB

76543210

Host PnP Address Low

76543210

A15

Host PnP Address High

Res PMICIE PMECIE PMHIE IBFCIE OBECIE OBFMIE OBFKIE

543

PSPE IRQNPOL

IRQM

IRQ11B IRQ12B IRQ1B

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