PC87570-ICCSLASHVUL datasheet(61/168 Pages) NSC

61 / 168 page

Host Bus Interface (HBI)

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5.14 HBI REGISTERS ACCESSED BY HOST

The PC87570 has 14 host-accessed registers that control

the host interface channel, listed with their indexes in Table

5-4.

Table 5-4. HBI Registers Accessed by Host

5.14.1

Identification Register (SID)

The SID Register identifies the chip. Its value is fixed as

00h. This register is a read only register. Data written to it is

ignored.

5.14.2

Identification Type Register (SIDT)

The SIDT Register identifies the chip type. Its value is fixed

as 01h for the PC87570. This register is a read only register.

Data written to it is ignored.

5.14.3

Identification Revision Register (SIDR)

The SIDR Register identifies the chip revision. Its value is

fixed as 00h for the first revision. This register is a read only

5.14.4

Base Address High Register (SBAH)

The SBAH Register holds the high address bits of the con-

figuration Index and Data Registers’ base address.

The value of this register after reset is undefined. It is initial-

ized by the motherboard PnP protocol, described in Section

5.13.

After this register has been initialized, the address may be

updated if SBALK in the FLR Register is 0. This change is

performed using the scheme described in “Changing the

Configuration Base Address” on page 60.

Bits 0 through 7 of this register hold the host bus address bits

8 through 15, respectively.

5.14.5

Base Address Low Register (SBAL)

The SBAL Register holds the low address byte of the con-

figuration Index and Data Registers’ base address.

The value of this register after reset is undefined. It is initial-

ized by the mother board PnP protocol, described in Section

5.13.

After this register has been initialized, the address may be

updated if SBALK in the FLR Register is 0. This change is

performed using the scheme described in “Changing the

Configuration Base Address” on page 60.

Bits 0 through 7 of this register hold the host bus address

bits 0 through 7, respectively. Bit 0 is a read only bit and

holds the value 0. Data written to this bit is ignored.

5.14.6

RTC Chip Select Address High Register (RTCCSAH)

The RTCCSAH Register holds the high address bits of the

RTC module. Bits 0 through 7 of this register hold the host

bus address bits 8 through 15, respectively. On reset, this

the FLR Register is 0.

5.14.7

RTC Chip Select Address Low Register (RTCCSAL)

The RTCCSAL Register holds the low address bits of the

RTC module. Bits 0 through 7 of this register hold the host

bus address bits 0 through 7, respectively. Bit 0 is a read

only bit and hold the value 0. This bit is ignored when de-

Mnemonic

Index

SID

Chip Identity Register

22h

SIDT

Chip Type Register

26h

SIDR

Chip Revision Register

27h

SBAH

Chip Base Address, High Register

4Bh

SBAL

Chip Base Address, Low Register

4Ah

RTCCSAH RTC Chip Select Address, High

(HRTCCS) Register

50h

RTCCSAL RTC Chip Select Address, Low

51h

KBCCSAH KBC Chip Select Address, High

(KKBCCS) Register

52h

KBCCSAL KBC Chip Select Address, Low

53h

PMCSAH

PM Chip Select Address, High

(HPMCS) Register

54h

PMCSAL

PM Chip Select Address, Low

55h

FER

Function Enable Register

56h

FLR

Function Lock Register

57h

IRQE

IRQ Enable Register

58h

76543210

MSB

ID Value

LSB

76543210

MSB

ID Value

LSB

76543210

MSB

ID Value

LSB

76543210

Address High HA15-8

76543210

Address Low HA7-0

76543210

Address High HA15-8

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