PC87570-ICCSLASHVUL datasheet(92/168 Pages) NSC

92 / 168 page

PS/2 Interface

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Start Bit Detected: The shift mechanism is in Receive Ac-

tive or Transmit Active states. This indicates that a start bit

was identified for at least one of the channels and the shift

process has begun. The PSTAT.SOT indicates the detec-

tion of the start bit and the PSTAT.ACH field indicates the

active channel (the channel on which the start bit was de-

tected).

End of Transaction: The shift mechanism is at “End-of-

Reception” or “End-of-Transmission” states. This indicates

that the last bit of the transfer sequence was detected and

the data can be read from PSDAT register, or that the data

transmission was completed (for receive and transmit, re-

spectively). The PSTAT.EOT indicates the transfer comple-

tion. In case a parity error was identified in the received

data, the PSTAT.PERR is set. If a stop bit was detected low

instead of high, the PSTAT.RFERR bit is set.

Input Signals Debounce

The PC87570 performs a debounce operation on the clock

input signal before determining its logic value. PSCON.IDB

determines for how many clock cycles the input signal must

be stable to define a change in its value.

Interrupt Generation

The PSINT1 is an interrupt signal generated by the shift

mechanism to allow an interrupt driven interface with the

firmware.

The ICU should be programmed to detect high level inter-

rupts on the PSINT1 interrupt. See Section 9.3 on page 82

for details on the ICU. The PSIEN.SOTIE and PSIEN.EO-

TIE mask the interrupt signaling for the PSTAT.SOT and

PSTAT.EOT bits respectively.

Receive Inactive

After enabling the shift mechanism with PSCON.XMT=0,

the Receive mode is entered in the Receive Inactive state.

The Receive Idle state can then be entered by enabling one

(or more) of the channels, through setting the channel en-

able bit (CLK1, CLK2 and/or CLK3 for channel 1, 2 and/or

3, respectively). In this state, the shift-mechanism sets the

clock and data lines of the enabled channels high (1) and

waits for a start bit.

PS/2 Reset

XMT = 0

XMT = 1

Start Bit

Detected

XMT = 1

EN = 1 and

EN = 0

Disabled

Receive

Inactive

XMT = 0

EN=1 and

Transmit

Idle

CLK1, CLK2

Transmit

Active

Line Control

Bit Detected

End of

Transmission

or CLK3 = 1

Start Bit

Detected

Receive

Idle

CLK1, CLK2

Receive

Active

Stop Bit

Detected

End of

Reception

and/or CLK3 = 1

Transmit Mode

Receive Mode

EN = 0

CLK1, CLK2

and CLK3 = 0

CLK1, CLK2

and CLK3 = 0

Transmit

Inactive

Figure 12-4. Shift Mechanism State Diagram

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