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PC87570-ICC/VUL датащи(PDF) 36 Page - National Semiconductor (TI) |
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PC87570-ICC/VUL датащи(HTML) 36 Page - National Semiconductor (TI) |
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36 / 168 page ![]() Bus Interface Unit (BIU) 36 www.national.com 3.3.3 Early Write Bus Cycle If the BCFG.EWR configuration bit is 1, the BIU uses early write bus cycles; this allows removal of the RD signal from the memory device interface. The basic early write bus cy- cle takes three clock cycles. The cycle starts at T1, when the data bus is in TRI-STATE and the address is placed on the address bus. RD is inac- tive to indicate that this is a write bus cycle; then WR0-1 are activated. At the first TIW, or T2 (when there are no TIW cycles), the data is placed on the data bus and the SELn (or SELIO) is activated. The bus transaction is terminated at T3, when SELn (or SELIO) becomes inactive; then WR0-1 become inactive and the data bus is put in TRI-STATE. The address remains valid until T3 is complete. Thold clock cycles may follow T3, according to SZCF- Gn.HOLD or IOCFG.HOLD (may be 0). The address and data remains valid until the end of the last Thold cycle. The data is put in TRI-STATE in the clock cycle after the last Thold or T3 (if no Thold cycle is configured). See Figures 3-1, 3-2 and 3-3. If a read bus cycle immediately follows an Early Write bus cycle, an idle cycle is added between the two. SZCFGn.HOLD ≠ 0 SZCFGn.WAIT ≠ 0 T2 SELn: inactive, WR0-1: inactive, If SZCFGn.HOLD = 0 data put in TRI-STATE. SZCFGn.WAIT = 0 Hold cycles completed Address placed on A0-15, WR(0-1): activated Data placed on D0-15, SELn: active Internal waits completed SZCFGn.HOLD=0 Address on A0-15 invalid/changed Data put in TRI-STATE Data placed on D0-15, SELn: active Internal waits corresponding to SZCFGn.WAIT T1 T2 Thold Hold cycles according to SZCFGn.HOLD TIW T3 T1 end begin Figure 3-1. Early Write Bus Cycle Note: Any reference to SZCFGn, also applies to the IOCFG Register. Any reference to SELn, also applies to the SELIO signal. |
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