PC87570-ICCSLASHVUL datasheet(6/168 Pages) NSC

6 / 168 page

Table of Contents

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5.7

PM CHANNEL ........................................................................................................................... 52

5.8

RTC/APC CHANNEL ................................................................................................................. 52

5.9

CR16A INTERRUPTS ............................................................................................................... 52

5.10

HOST INTERRUPTS ................................................................................................................. 52

5.10.1

IRQ1, IRQ12 and IRQ11 and IRQ8 Buffers ................................................................. 53

5.11

SYSTEM CONSIDERATIONS ................................................................................................... 53

5.11.1

Reset Configuration ..................................................................................................... 53

5.11.2

Host Power-On (HPWRON) Indication Input ............................................................... 53

5.11.3

Host Master Reset (HMR) Input .................................................................................. 53

5.11.4

Host Reset Output (HRSTO) from PC87570 ............................................................... 53

5.11.5

HDEN Strap ................................................................................................................. 54

5.11.6

GA20 Pin Functionality ................................................................................................ 54

5.11.7

Host Driven Wake-Up .................................................................................................. 54

5.11.8

APC-ON and APC-OFF Events ................................................................................... 54

5.12

HBI REGISTERS ACCESSED BY CR16A ................................................................................ 54

5.12.1

Control and Status Register 1 (CST1) ......................................................................... 55

5.12.2

Control and Status Register 2 (CST2) ......................................................................... 55

5.12.3

RTC Core Address Register (RTCCA) ........................................................................ 55

5.12.4

RTC Core Data Register (RTCCD) ............................................................................. 56

5.12.5

Host PnP Initial Configuration Base Address Low and High Registers (HCFGBAL/H) 56

5.12.6

Host Interface Control Register (HICTRL) ................................................................... 56

5.12.7

Host Interface IRQ Control Register (HIIRQC) ............................................................ 56

5.12.8

Host Interface KBC Status Register (HIKMST) ........................................................... 57

5.12.9

Host Interface Keyboard Data Out Buffer Register (HIKDO) ....................................... 57

5.12.10 Host Interface Mouse Data Out Buffer Register (HIMDO) ........................................... 58

5.12.11 Host Interface KBC Data In Buffer Register (HIKMDI) ................................................ 58

5.12.12 Host Interface PM Port Status Register (HIPMST) ...................................................... 58

5.12.13 Host Interface PM Data Out Buffer Register (HIPMDO) .............................................. 58

5.12.14 Host Interface PM Data In Buffer Register (HIPMDI) .................................................. 58

5.13

HOST CHANNEL CONFIGURATION ....................................................................................... 58

5.13.1

Chip Base Address Initial Setting ................................................................................ 58

5.13.2

Operation Guidelines ................................................................................................... 60

5.14

HBI REGISTERS ACCESSED BY HOST ................................................................................. 61

5.14.1

Identification Register (SID) ......................................................................................... 61

5.14.2

Identification Type Register (SIDT) ............................................................................. 61

5.14.3

Identification Revision Register (SIDR) ....................................................................... 61

5.14.4

Base Address High Register (SBAH) .......................................................................... 61

5.14.5

Base Address Low Register (SBAL) ............................................................................ 61

5.14.6

RTC Chip Select Address High Register (RTCCSAH) ................................................ 61

5.14.7

RTC Chip Select Address Low Register (RTCCSAL) ................................................. 61

5.14.8

KBC Chip Select Address High Register (KBCCSAH) ................................................ 62

5.14.9

KBC Chip Select Address Low Register (KBCCSAL) ................................................. 62

5.14.10 PM Chip Select Address High Register (PMCSAH) .................................................... 62

5.14.11 PM Chip Select Address Low Register (PMCSAL) ..................................................... 62

5.14.12 Function Enable Register (FER) .................................................................................. 62

5.14.13 Function Lock Register (FLR) ...................................................................................... 63

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