SC16C752B datasheet(29/47 Pages) PHILIPS

29 / 47 page

Philips Semiconductors

SC16C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Product data

Rev. 03 — 14 December 2004

29 of 47

9397 750 14443

7.11 Divisor latches (DLL, DLH)

These are two 8-bit registers which store the 16-bit divisor for generation of the baud

clock in the baud rate generator. DLH stores the most signiﬁcant part of the divisor.

DLL stores the least signiﬁcant part of the divisor.

Note that DLL and DLH can only be written to before sleep mode is enabled, i.e.,

before IER[4] is set.

7.12 Transmission control register (TCR)

This 8-bit register is used to store the RX FIFO threshold levels to stop/start

transmission during hardware/software ﬂow control. Table 20 shows transmission

control register bit settings.

TCR trigger levels are available from 0-60 bytes with a granularity of four.

Remark: TCR can only be written to when EFR[4] = 1 and MCR[6] = 1. The

programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is no

built-in hardware check to make sure this condition is met. Also, the TCR must be

programmed with this condition before Auto-RTS or software ﬂow control is enabled

to avoid spurious operation of the device.

7.13 Trigger level register (TLR)

This 8-bit register is pulsed to store the transmit and received FIFO trigger levels

used for DMA and interrupt generation. Trigger levels from 4-60 can be programmed

with a granularity of 4. Table 21 shows trigger level register bit settings.

Remark: TLR can only be written to when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or

TLR[7:4] are logical 0, the selectable trigger levels via the FIFO control register (FCR)

are used for the transmit and receive FIFO trigger levels. Trigger levels from 4-60

bytes are available with a granularity of four. The TLR should be programmed for N

⁄4,

where N is the desired trigger level.

When the trigger level setting in TLR is zero, the SC16C752B uses the trigger level

setting deﬁned in FCR. If TLR has non-zero trigger level value, the trigger level

deﬁned in FCR is discarded. This applies to both transmit FIFO and receive FIFO

trigger level setting.

When TLR is used for RX trigger level control, FCR[7:6] should be left at the default

state, i.e., ‘00’.

Table 20:

Transmission Control Register bits description

Bit

Symbol

Description

7:4

TCR[7:4]

RX FIFO trigger level to resume transmission (0-60).

3:0

TCR[3:0]

RX FIFO trigger level to halt transmission (0-60).

Table 21:

Trigger Level Register bits description

Bit

Symbol

Description

7:4

TLR[7:4]

RX FIFO trigger levels (4-60), number of characters available.

3:0

TLR[3:0]

TX FIFO trigger levels (4-60), number of spaces available.

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