SC16C752B datasheet(28/47 Pages) PHILIPS

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Philips Semiconductors

SC16C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Product data

Rev. 03 — 14 December 2004

28 of 47

9397 750 14443

7.10 Enhanced feature register (EFR)

This 8-bit register enables or disables the enhanced features of the UART. Table 19

shows the enhanced feature register bit settings.

Table 18:

Interrupt priority list

Priority

level

IIR[5]

IIR[4]

IIR[3]

IIR[2]

IIR[1]

IIR[0]

Source of the interrupt

00110

Receiver Line Status error

01100

Receiver time-out interrupt

00100

RHR interrupt

00010

THR interrupt

00000

Modem interrupt

10000

Received Xoff signal/

special character

00000

CTS, RTS change of state

from active (LOW) to

inactive (HIGH)

Table 19:

Enhanced Feature Register bits description

Bit

Symbol

Description

EFR[7]

CTS ﬂow control enable.

Logic 0 = CTS ﬂow control is disabled (normal default condition).

Logic 1 = CTS ﬂow control is enabled. Transmission will stop when a

HIGH signal is detected on the CTS pin.

EFR[6]

RTS ﬂow control enable.

Logic 0 = RTS ﬂow control is disabled (normal default condition).

Logic 1 = RTS ﬂow control is enabled. The RTS pin goes HIGH when

the receiver FIFO HALT trigger level TCR[3:0] is reached, and goes

LOW when the receiver FIFO RESUME transmission trigger level

TCR[7:4] is reached.

EFR[5]

Special character detect.

Logic 0 = Special character detect disabled (normal default condition).

Logic 1 = Special character detect enabled. Received data is

compared with Xoff-2 data. If a match occurs, the received data is

transferred to FIFO and IIR[4] is set to a logical 1 to indicate a special

character has been detected.

EFR[4]

Enhanced functions enable bit.

Logic 0 = Disables enhanced functions and writing to IER[7:4],

FCR[5:4], MCR[7:5].

Logic 1 = Enables the enhanced function IER[7:4], FCR[5:4], and

MCR[7:5] can be modiﬁed, i.e., this bit is therefore a write enable.

3:0

EFR[3:0]

Combinations of software ﬂow control can be selected by programming

these bits. See Table 3 “Software ﬂow control options (EFR[0:3])” on

page 9.

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