SC16C752B datasheet(26/47 Pages) PHILIPS

26 / 47 page

Philips Semiconductors

SC16C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Product data

Rev. 03 — 14 December 2004

26 of 47

9397 750 14443

7.7 Modem status register (MSR)

This 8-bit register provides information about the current state of the control lines

from the mode, data set, or peripheral device to the processor. It also indicates when

a control input from the modem changes state. Table 15 shows modem status

[1]

The primary inputs RI, CD, CTS, DSR are all Active-LOW, but their registered equivalents in the MSR

and MCR (in loop-back) registers are Active-HIGH.

7.8 Interrupt enable register (IER)

The interrupt enable register (IER) enables each of the six types of interrupt, receiver

error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from

LOW to HIGH. The INT output signal is activated in response to interrupt generation.

Table 16 shows interrupt enable register bit settings.

Table 15:

Modem Status Register bits description

Bit

Symbol

Description

MSR[7]

CD (Active-HIGH, logical 1). This bit is the complement of the CD input

during normal mode. During internal loop-back mode, it is equivalent to

MCR[3].

MSR[6]

RI (Active-HIGH, logical 1). This bit is the complement of the RI input

during normal mode. During internal loop-back mode, it is equivalent to

MCR[2].

MSR[5]

DSR (Active-HIGH, logical 1). This bit is the complement of the DSR

input during normal mode. During internal loop-back mode, it is

equivalent MCR[0].

MSR[4]

CTS (Active-HIGH, logical 1). This bit is the complement of the CTS

input during normal mode. During internal loop-back mode, it is

equivalent to MCR[1].

MSR[3]

∆CD. Indicates that CD input (or MCR[3] in loop-back mode) has

changed state. Cleared on a read.

MSR[2]

∆RI. Indicates that RI input (or MCR[2] in loop-back mode) has changed

state from LOW to HIGH. Cleared on a read.

MSR[1]

∆DSR. Indicates that DSR input (or MCR[0] in loop-back mode) has

changed state. Cleared on a read.

MSR[0]

∆CTS. Indicates that CTS input (or MCR[1] in loop-back mode) has

changed state. Cleared on a read.

Table 16:

Interrupt Enable Register bits description

Bit

Symbol

Description

IER[7] [1]

CTS interrupt enable.

Logic 0 = Disable the CTS interrupt (normal default condition).

Logic 1 = Enable the CTS interrupt.

IER[6] [1]

RTS interrupt enable.

Logic 0 = Disable the RTS interrupt (normal default condition).

Logic 1 = Enable the RTS interrupt.

IER[5] [1]

Xoff interrupt.

Logic 0 = Disable the Xoff interrupt (normal default condition).

Logic 1 = Enable the Xoff interrupt.

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