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SC16C752B датащи(PDF) 6 Page - NXP Semiconductors

номер детали SC16C752B
подробное описание детали  5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
PDF  47 Pages
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производитель  PHILIPS [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

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Philips Semiconductors
SC16C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Product data
Rev. 03 — 14 December 2004
6 of 47
9397 750 14443
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
OPA, OPB
32, 9
22, 7
O
User defined outputs. This function is associated with individual channels A
and B. The state of these pins is defined by the user through the software
settings of MCR[3]. INTA-INTB are set to active mode and OPA-OPB to a
logic 0 when MCR[3] is set to a logic 1. INTA-INTB are set to the 3-State
mode and OPA-OPB to a logic 1 when MCR[3] is set to a logic 0. The output
of these two pins is HIGH after reset.
RESET
36
24
I
Reset. This pin will reset the internal registers and all the outputs. The UART
transmitter output and the receiver input will be disabled during reset time.
RESET is an active-HIGH input.
RIA, RIB
41, 21
-
I
Ring Indicator (Active-LOW). These inputs are associated with individual
UART channels, A and B. A logic 0 on these pins indicates the modem has
received a ringing signal from the telephone line. A LOW-to-HIGH transition
on these input pins generates a modem status interrupt, if enabled. The state
of these inputs is reflected in the modem status register (MSR).
RTSA,
RTSB
33, 22
23, 15
O
Request to Send (Active-LOW). These outputs are associated with
individual UART channels, A and B. A logic 0 on the RTS pin indicates the
transmitter has data ready and waiting to send. Writing a logic 1 in the
modem control register MCR[1] will set this pin to a logic 0, indicating data is
available. After a reset these pins are set to a logic 1. These pins only affect
the transmit and receive operations when Auto-RTS function is enabled via
the Enhanced Feature Register (EFR[6]) for hardware flow control operation.
RXA, RXB
5, 4
4, 3
I
Receive data input. These inputs are associated with individual serial
channel data to the SC16C752B. During the local loop-back mode, these RX
input pins are disabled and TX data is connected to the UART RX input
internally.
RXRDYA,
RXRDYB
31, 18
-
O
Receive Ready (Active-LOW). RXRDYA or RXRDYB goes LOW when the
trigger level has been reached or the FIFO has at least one character. It goes
HIGH when the RX FIFO is empty.
TXA, TXB
7, 8
5, 6
O
Transmit data A, B. These outputs are associated with individual serial
transmit channel data from the SC16C752B. During the local loop-back
mode, the TX output pin is disabled and TX data is internally connected to
the UART RX input.
TXRDYA,
TXRDYB
43, 6
-
O
Transmit Ready (Active-LOW). TXRDYA or TXRDYB go LOW when there
are at least a trigger level number of spaces available or when the FIFO is
empty. It goes HIGH when the FIFO is full or not empty.
VCC
42
26
I
Power supply input.
XTAL1
13
10
I
Crystal or external clock input. Functions as a crystal input or as an
external clock input. A crystal can be connected between XTAL1 and XTAL2
to form an internal oscillator circuit (see Figure 13). Alternatively, an external
clock can be connected to this pin to provide custom data rates.
XTAL2
14
11
O
Output of the crystal oscillator or buffered clock. (See also XTAL1.)
XTAL2 is used as a crystal oscillator output or a buffered clock output.
Table 2:
Pin description…continued
Symbol
Pin
Type
Description
LQFP48 HVQFN32



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