SC16C752B datasheet(21/47 Pages) PHILIPS

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Philips Semiconductors

SC16C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Product data

Rev. 03 — 14 December 2004

21 of 47

9397 750 14443

[3]

The Special Register set is accessible only when LCR[7] is set to a logic 1.

[4]

Enhanced Feature Register; Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BFHex’.

Remark: Refer to the notes under Table 9 for more register access information.

7.1 Receiver holding register (RHR)

The receiver section consists of the receiver holding register (RHR) and the receiver

shift register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial

data from the RX terminal. The data is converted to parallel data and moved to the

RHR. The receiver section is controlled by the line control register. If the FIFO is

disabled, location zero of the FIFO is used to store the characters.

Remark: In this case, characters are overwritten if overﬂow occurs.

If overﬂow occurs, characters are lost. The RHR also stores the error status bits

associated with each character.

7.2 Transmit holding register (THR)

The transmitter section consists of the transmit holding register (THR) and the

transmit shift register (TSR). The THR is actually a 64-byte FIFO. The THR receives

data and shifts it into the TSR, where it is converted to serial data and moved out on

the TX terminal. If the FIFO is disabled, the FIFO is still used to store the byte.

Characters are lost if overﬂow occurs.

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