SC16C752B datasheet(27/47 Pages) PHILIPS

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Philips Semiconductors

SC16C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Product data

Rev. 03 — 14 December 2004

27 of 47

9397 750 14443

[1]

IER[7:4] can only be modiﬁed if EFR[4] is set, i.e., EFR[4] is a write enable. Re-enabling IER[1] will

not cause a new interrupt if the THR is below the threshold.

7.9 Interrupt identiﬁcation register (IIR)

The IIR is a read-only 8-bit register which provides the source of the interrupt in a

prioritized manner. Table 17 shows interrupt identiﬁcation register bit settings.

The interrupt priority list is shown in Table 18.

IER[4] [1]

Sleep mode.

Logic 0 = Disable sleep mode (normal default condition).

Logic 1 = Enable sleep mode. See Section 6.7 “Sleep mode” for details.

IER[3]

Modem Status Interrupt.

Logic 0 = Disable the modem status register interrupt (normal default

condition).

Logic 1 = Enable the modem status register interrupt.

IER[2]

Receive Line Status interrupt.

Logic 0 = Disable the receiver line status interrupt (normal default

condition).

Logic 1 = Enable the receiver line status interrupt.

IER[1]

Transmit Holding Register interrupt.

Logic 0 = Disable the THR interrupt (normal default condition).

Logic 1 = Enable the THR interrupt.

IER[0]

Receive Holding Register interrupt.

Logic 0 = Disable the RHR interrupt (normal default condition).

Logic 1 = Enable the RHR interrupt.

Table 16:

Interrupt Enable Register bits description…continued

Bit

Symbol

Description

Table 17:

Interrupt Identiﬁcation Register bits description

Bit

Symbol

Description

7:6

IIR[7:6]

Mirror the contents of FCR[0].

IIR[5]

RTS/CTS LOW-to-HIGH change of state.

IIR[4]

1 = Xoff/Special character has been detected.

3:1

IIR[3:1]

3-bit encoded interrupt. See Table 18.

IIR[0]

Interrupt status.

Logic 0 = An interrupt is pending.

Logic 1 = No interrupt is pending.

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