AD9528 datasheet(34/68 Pages) AD

34 / 68 page

Data Sheet

AD9528

Rev. C | Page 33 of 67

SYSREF Mode 2: External with Retiming

Figure 38 shows the SYSREF clock path with Mode 2 selected.

Apply a differential or single-ended SYSREF clock signal to the

SYSREF_IN and SYSREF_IN pins (see Mode 1).

Unlike Mode 1, Mode 2 retimes the external SYSREF signal

either with the signal originating at the VCXO_IN

and VCXO_IN pins (Pin 11 and Pin 12, respectively), or with

the signal at the feedback node of PLL2. Register 0x0402, Bit 4

selects the source that retimes the external SYSREF signal. Note

that the SYSREF_REQ pin and Bit 0 of Register 0x0403 (SPI

SYSREF Request) are unused in Mode 2.

SYSREF Mode 3: Internal

Figure 39 shows the SYSREF clock path with Mode 3 selected.

Mode 3 uses the internal SYSREF pattern generator and the

SYSREF request feature to produce a user defined SYSREF

signal. A SYSREF request can be made via hardware (the

SYSREF_REQ pin) or software (Register 0x0403, Bit 0, the SPI

SYSREF request bit). In internal SYSREF mode, the PLLs must

be locked before the SYSREF request signal is used.

Figure 38. Mode 2, Retimes the External SYSREF to the Internal VCXO or PLL2 Input Divider Output and then Routes to the Clock Distribution Output(s)

Figure 39. Mode 3, SYSREF Generated Internally and Routed to the Clock Distribution

CONTROL

INTERFACE

(SPI AND I2C)

SYSREF GENERATION

SPI SYSREF

REQUEST

LOCK

DETECT

SYSREF

GENERATION

TRIGGER

AD9528

VCXO_IN PLL2 DIVIDER

SYSREF_REQ

D Q

SYSREF_IN

CLOCK

DISTRIBUTION

CONTROL

INTERFACE

(SDI AND I2C)

SYSREF GENERATION

SPI SYSREF

REQUEST

LOCK

DETECT

SYSREF

GENERATION

TRIGGER

AD9528

VCXO_IN PLL2 DIVIDER

SYSREF_REQ

D Q

SYSREF_IN

CLOCK

DISTRIBUTION

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