AD9528 datasheet(33/68 Pages) AD

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AD9528

Data Sheet

Rev. C | Page 32 of 67

SYSREF OPERATION

The AD9528 supports the JESD204B standard for synchronizing

high speed converters and logic devices such as FPGAs by

providing paired device clock and SYSREF clock signals. The

SYSREF clock or device clock can be distributed to any one or

more of the 14 outputs via the clock distribution section within

the AD9528. After the SYSREF clock reaches the clock distribution

section, programmable digital coarse delay and/or analog fine

delay is available to adjust timing between the SYSREF clock

with respect to the device clock. The delay establishes proper

setup and hold timing downstream between device clock and

SYSREF clock at the inputs of the converter(s) or logic device(s).

SYSREF SIGNAL PATH

The AD9528 provides two sources for the purpose of generating

a SYSREF signal. The first source is a user provided external

SYSREF clock signal applied to SYSREF_IN and SYSREF_IN

(Pin 70 and Pin 71, respectively). The second source is an

internal SYSREF generation circuit that enables the user to

specify an internally generated pulse pattern. There are three

modes of operation associated with the two sources as defined

by Register 0x0403, Bits[7:6].

•

00 = Mode 1 (external SYSREF)

•

01 = Mode 2 (external SYSREF resampled by the VCXO or

PLL2 feedback divider)

•

1x = Mode 3 (internally generated SYSREF).

SYSREF Mode 1: External

Figure 37 shows the SYSREF clock path with Mode 1 selected.

Apply an external SYSREF clock signal to the SYSREF_IN

and/or SYSREF_IN pin(s). A single-ended signal may be

applied to either pin separately or a differential signal may be

applied across both pins. Note that the SYSREF_REQ pin and

Bit 0 of Register 0x0403 (SPI SYSREF Request) are unused in

Mode 1.

Figure 37. Mode 1, Routes the External SYSREF Directly to the Clock Distribution Output(s)

CONTROL

INTERFACE

(SPI AND I2C)

SYSREF GENERATION

CLOCK

DISTRIBUTION

SPI SYSREF

REQUEST

LOCK

DETECT

SYSREF

GENERATION

TRIGGER

AD9528

VCXO_IN PLL2 DIVIDER

SYSREF_REQ

D Q

SYSREF_IN

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