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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9528 датащи(PDF) 32 Page - Analog Devices |
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AD9528 датащи(HTML) 32 Page - Analog Devices |
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32 / 68 page  Data Sheet AD9528 Rev. C | Page 31 of 67 Clock Distribution Synchronization A block diagram of the clock distribution synchronization functionality is shown in Figure 35. The synchronization feature edge aligns all outputs together or to forces a desired phase offset between output edges. An automatic synchronization of the channel dividers is initiated the first time the PLL2 locks after a power-up or reset event. Subsequent lock and unlock events do not initiate a resynchronization unless preceded by a power- down or reset of the device. All outputs are disabled temporarily while the sync output bit in Register 0x032A, Bit 0 is active, unless the channel is programmed to ignore the sync output command. The ignore sync command for each channel is controlled via Register 0x032B and Register 0x032C. When using the sync output bit to synchronize outputs, first set and then clear the bit. The synchronization event is the clearing operation (that is, the Logic 1 to Logic 0 transition of the bit). The channel dividers are automatically synchronized to each other when PLL2 is ready. In normal operation, the phase offsets are already programmed through the SPI/I2C port before the AD9528 starts to provide outputs. Although the digital coarse phase offsets cannot be adjusted while the dividers are operating, it is possible to adjust the phase of all outputs relative to each other without powering down PLL1 and PLL2. This is accomplished by programming the new phase offset using Bits[5:0] in the clock distribution registers, and then issuing an output sync by using the sync outputs bit (Register 0x032A, Bit 0). Figure 35. Clock Distribution Synchronization Block Diagram Figure 36. Clock Output Synchronization Timing Diagram FAN OUT VCO RF DIVIDER SYNC OUTPUT BIT DIVIDER DRIVER OUTx OUTx OUT SYNC PHASE DIVIDE DIVIDE = 2, PHASE = 0 DIVIDE = 2, PHASE = 6 VCO DIVIDER OUTPUT CLOCK SYNC OUTPUTS 6 × 0.5 PERIODS |
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