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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9528 датащи(PDF) 17 Page - Analog Devices |
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AD9528 датащи(HTML) 17 Page - Analog Devices |
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17 / 68 page  AD9528 Data Sheet Rev. C | Page 16 of 67 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 21. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1 VDD P 3.3 V Supply for the PLL1 Input Section. 2 REFA I Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 3 REFA I Complementary Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 4 REF_SEL I Reference Input Select. The reference input selection function defaults to software control via internal Register 0x010A, Bits[2:0]. When the REF_SEL pin is active, a logic low selects REFA and logic high selects REFB. 5 REFB I Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 6 REFB I Complementary Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 7 LF1 O PLL1 External Loop Filter. 8 VCXO_VT O VCXO Control Voltage. Connect this pin to the voltage control pin of the external VCXO. 9 NIC NIC No Internal Connection. The pin can be left floating. 10 VDD P 3.3 V Supply for the PLL2 Section. 11 VCXO_IN I PLL1 Oscillator Input. Along with VCXO_IN, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 12 VCXO_IN I Complementary PLL1 Oscillator Input. Along with VCXO_IN, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 13 NIC NIC No Internal Connection. The pin can be left floating. 14 LF2_CAP O PLL2 External Loop Filter Capacitor Connection. Connect capacitor between this pin and the LDO_VCO pin. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD REFA REFA REF_SEL REFB REFB LF1 VCXO_VT NIC VDD VCXO_IN VCXO_IN NIC LF2_CAP LDO_VCO VDD 17 NIC 18 NIC 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 VDD4 OUT4 OUT4 VDD5 OUT5 OUT5 VDD6 OUT6 OUT6 VDD7 OUT7 OUT7 VDD8 OUT8 OUT8 VDD9 OUT9 OUT9 NOTES 1. NIC = NO INTERNAL CONNECTION. THIS PIN CAN BE LEFT FLOATING. 2. THE EXPOSED PAD IS THE GROUND CONNECTION ON THE CHIP. IT MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. AD9528 TOP VIEW (Not to Scale) |
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