AD9528 datasheet(52/68 Pages) AD

52 / 68 page

Data Sheet

AD9528

Rev. C | Page 51 of 67

Addr

(Hex)

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Value

(Hex)

Power-Down Control

0x0500

Power-down control

enable

Reserved

Bias generation

power-down

disable

or power-down

PLL2 power-

down enable

PLL1 power-

down enable

Clock

distribution

power-down

enable

Chip power-

down enable

0x10

0x0501

Output channel

power down enable

Channel 7

power-down

Channel 6

power-down

Channel 5

power-down

Channel 4

power-down

Channel 3

power-down

Channel 2

power-down

Channel 1

power-down

Channel 0

power-down

0x00

0x0502

Reserved

Channel 13

power-down

Channel 12

power-down

Channel 11

power-down

Channel 10

power-down

Channel 9

power-down

Channel 8

power-down

0x00

0x0503

LDO regulator enable Channel 7

LDO enable

Channel 6

LDO enable

Channel 5

LDO enable

Channel 4 LDO

enable

Channel 3

LDO enable

Channel 2

LDO enable

Channel 1

LDO enable

Channel 0

LDO enable

0xFF

0x0504

PLL2 LDO

enable

PLL1 LDO

enable

Channel 13

LDO enable

Channel 12

LDO enable

Channel 11

LDO enable

Channel 10

LDO enable

Channel 9

LDO enable

Channel 8

LDO enable

0xFF

Status and Status Readback5

0x0505

Status control signals

Status Monitor 0 Control, Bits[7:0]

0x00

0x0506

Status Monitor 1 Control, Bits[7:0]

0x00

0x0507

Status pin enable and

status divider enable

Reserved

STATUS1 pin

output enable

STATUS0 pin

output enable

STATUS0

divider enable

STATUS1

divider enable

0x00

0x0508

Status Readback 0

PLL2 feedback

status

PLL1 feedback

status

VCXO status

Both

REFA/REFB

missing

REFB status

REFA status

PLL2 locked

status

PLL1 locked

status

0x00

0x0509

Status Readback 1

Reserved

Holdover

active status

Selected

reference

Fast lock in

progress

VCO

calibration

busy status

0x00

1 The soft reset bits (Bit 0 and Bit 7) are logically AND gated internally; therefore, set or clear both bits together.

2 The LSB first bits (Bit 1 and Bit 6) are logically AND gated internally; therefore, set or clear both bits together.

3 The address ascension bits (Bit 2 and Bit 5) are logically AND gated internally; therefore, set or clear both bits together.

4 The SDO active bits (Bit 3 and Bit 4) are logically AND gated internally; therefore, set or clear both bits together.

5 Register 0x0505, Register 0x0506, and Register 0x0507 are control status pins as notated by bit names 0x0505 (Status 0) and 0x0506 (Status 1). Register 0x0508 and

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