AD9528 datasheet(39/68 Pages) AD

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AD9528

Data Sheet

Rev. C | Page 38 of 67

I2C SERIAL PORT OPERATION

The I2C interface is popular because it requires only two pins

and easily supports multiple devices on the same bus. Its main

disadvantage is programming speed, which is 400 kbps

(maximum). The AD9528 I2C port design uses the I2C fast

mode; however, it supports both the 100 kHz standard mode

and 400 kHz fast mode.

The AD9528 does not strictly adhere to every requirement in

the original I2C specification. In particular, specifications such

as slew rate limiting and glitch filtering are not implemented.

Therefore, the AD9528 is I2C compatible, but may not be fully

I2C compliant.

The AD9528 I2C port consists of a serial data line (SDA) and a

serial clock line (SCL). In an I2C bus system, the AD9528 is

connected to the serial bus (data bus SDA and clock bus SCL) as

a slave device; that is, no clock is generated by the AD9528. The

AD9528 uses direct 16-bit memory addressing instead of more

common 8-bit memory addressing.

The AD9528 allows up to three unique slave devices to occupy

the I2C bus. These are accessed via a 7-bit slave address

transmitted as part of an I2C packet. Only the device with a

matching slave address responds to subsequent I2C commands.

Table 24 lists the supported device slave addresses.

I2C Bus Characteristics

A summary of the various I2C abbreviations appears in Table 28.

Table 28. I2C Bus Abbreviation Definitions

Abbreviation

Definition

Start

Repeated start

Stop

Acknowledge

No acknowledge

Write

Read

The transfer of data is shown in Figure 46. One clock pulse is

generated for each data bit transferred. The data on the SDA

line must be stable during the high period of the clock. The

high or low state of the data line can change only when the

clock signal on the SCL line is low.

Figure 46. Valid Bit Transfer

Start/stop functionality is shown in Figure 47. The start

condition is characterized by a high to low transition on the

SDA line while SCL is high. The master always generates the

start condition to initialize a data transfer. The stop condition is

characterized by a low to high transition on the SDA line while

SCL is high. The master always generates the stop condition to

terminate a data transfer. Every byte on the SDA line must be

eight bits long. Each byte must be followed by an acknowledge

bit; bytes are sent MSB first.

The acknowledge bit (A) is the ninth bit attached to any 8-bit

data byte. An acknowledge bit is always generated by the

receiving device (receiver) to inform the transmitter that the

byte has been received by pulling the SDA line low during the

ninth clock pulse after each 8-bit data byte.

The no acknowledge bit (A) is the ninth bit attached to any

8-bit data byte. A no acknowledge bit is always generated by the

receiving device (receiver) to inform the transmitter that the

byte has not been received by leaving the SDA line high during

the ninth clock pulse after each 8-bit data byte. After issuing a

no acknowledge bit, the AD9528 I2C state machine goes into an

idle state.

Data Transfer Process

The master initiates data transfer by asserting a start condition,

which indicates that a data stream follows. All I2C slave devices

connected to the serial bus respond to the start condition.

The master then sends an 8-bit address byte over the SDA line,

consisting of a 7-bit slave address (MSB first) plus an R/W bit.

This bit determines the direction of the data transfer, that is,

whether data is written to or read from the slave device (0 =

write and 1 = read).

The peripheral whose address corresponds to the transmitted

address responds by sending an acknowledge bit. All other

devices on the bus remain idle while the selected device waits

for data to be read from or written to it. If the R/W bit is 0, the

master (transmitter) writes to the slave device (receiver). If the

R/W bit is 1, the master (receiver) reads from the slave device

(transmitter).

The format for these commands is described in the Data

Transfer Format section.

Data is then sent over the serial bus in the format of nine clock

pulses, one data byte (eight bits) from either master (write

mode) or slave (read mode) followed by an acknowledge bit

from the receiving device. The number of bytes that can be

transmitted per transfer is unrestricted. In write mode, the first

two data bytes immediately after the slave address byte are the

internal memory (control registers) address bytes, with the high

address byte first. This addressing scheme gives a memory

address of up to 216 − 1 = 65,535. The data bytes after these two

memory address bytes are register data written to the control

registers. In read mode, the data bytes after the slave address

byte are register data written to or read from the control

registers.

DATA LINE

STABLE;

DATA VALID

CHANGE

OF DATA

ALLOWED

SDA

SCL

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